HI5710A 查看數據表（PDF） - Intersil

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HI5710A

10-Bit, 20 MSPS A/D Converter

Intersil 

HI5710A

Timing Definitions

Dynamic Performance Definitions

Sampling Delay, is the time delay between the external

sample command (the rising edge of the clock) and the time

at which the analog input signal is actually sampled. This

delay is due to internal clock path propagation delays.

Data Latency, after the analog sample is taken, the digital

representation is output on the digital data output bus after

the 3rd cycle of the clock. This is due to the pipeline nature

of the converter where the data has to ripple through the

stages. This delay is specified as the data latency. After the

data latency time, the data representing each succeeding

analog input sample is output on the following rising edge of

the clock pulse. The digital data output lags the analog input

sample by 3 sampling clock cycles.

Power-up Initialization, this time is defined as the

maximum number of clock cycles that are required to

initialize the converter at power-up. The requirement arises

from the need to initialize some dynamic circuits within the

converter.

Static Performance Definitions

Differential Linearity Error, DNL, is the worst case

deviation of a code width from the ideal value of 1 LSB. The

converter is guaranteed to have no missing codes over the

operating temperature range.

Integral Linearity Error, INL, is the worst case deviation of

a code center from a best fit straight line calculated from the

measured data.

Fast Fourier Transform (FFT) techniques are used to

evaluate the dynamic performance of the HI5710A. A low

distortion sine wave is applied to the input, it is sampled, and

the output is stored in RAM. The data is then transformed

into the frequency domain with a 2048 point FFT and ana-

lyzed to evaluate the dynamic performance of the A/D. The

analog sine wave input signal to the converter is -0.5dB

down from full scale for all these tests. The distortion num-

bers are quoted in dBc (decibels with respect to carrier) and

DO NOT include any correction factors for normalizing to full

scale.

Signal-to-Noise Ratio, SNR, is the measured RMS signal

to RMS noise for a specified analog input frequency and

sampling frequency. The noise is the RMS sum of all of the

spectral components excluding the fundamental and the first

five harmonics.

Signal-to-Noise + Distortion Ratio, SINAD, is the measured

RMS signal to RMS sum of all other spectral components

below the Nyquist frequency excluding DC.

Effective Number Of Bits, ENOB, the effective number of

bits (ENOB) is calculated from the measured SINAD data.

as follows:

ENOB = (SINAD - 1.76 + VCORR) / 6.02,

where: VCORR = 0.5dB.

VCORR adjusts the ENOB for the amount the analog input

signal is below full scale.

2nd and 3rd Harmonic Distortion, is the ratio of the RMS

value of the 2nd and 3rd harmonic component, respectively,

to the RMS value of the measured input signal.

Analog Input Bandwidth, is the frequency at which the

amplitude of the digitally reconstructed output has

decreased 3dB below the amplitude of the input sine wave.

The input sine wave has a peak-to-peak amplitude equal to

the differential reference voltage. The bandwidth given is

measured at the specified sampling frequency.

4-1548

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