PC85132/232-1 查看數據表（PDF） - NXP Semiconductors.

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PC85132/232-1

LCD driver for low multiplex rates

NXP Semiconductors. 

NXP Semiconductors

PCA85132

LCD driver for low multiplex rates

25. Figures

Fig 1. Block diagram of PCA85132 . . . . . . . . . . . . . . . . .3

Fig 2. Pinning diagram of PCA85132 . . . . . . . . . . . . . . .4

Fig 3. Frequency generation of the PCA85132 . . . . . . . .9

Fig 4. Example of displays suitable for PCA85132 . . . .12

Fig 5. Typical system configuration . . . . . . . . . . . . . . . .12

Fig 6. Electro-optical characteristic: relative

transmission curve of the liquid . . . . . . . . . . . . . .15

Fig 7. Static drive mode waveforms . . . . . . . . . . . . . . . .16

Fig 8. Waveforms for the 1:2 multiplex drive mode

with 1⁄2 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Fig 9. Waveforms for the 1:2 multiplex drive mode

with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Fig 10. Waveforms for the 1:3 multiplex drive mode

with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Fig 11. Waveforms for the 1:4 multiplex drive mode

with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Fig 12. Display RAM bitmap . . . . . . . . . . . . . . . . . . . . . .22

Fig 13. Relationships between LCD layout, drive mode,

display RAM filling order, and display data

transmitted over the I2C-bus . . . . . . . . . . . . . . . .23

Fig 14. RAM banks in static and multiplex driving

mode 1:2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Fig 15. Bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Fig 16. Example of the Bank-select command with

multiplex drive mode 1:2 . . . . . . . . . . . . . . . . . . .27

Fig 17. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Fig 18. Definition of START and STOP conditions. . . . . .28

Fig 19. System configuration . . . . . . . . . . . . . . . . . . . . . .29

Fig 20. Acknowledgement on the I2C-bus . . . . . . . . . . . .29

Fig 21. I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . .31

Fig 22. Control byte format . . . . . . . . . . . . . . . . . . . . . . .31

Fig 23. Device protection diagram . . . . . . . . . . . . . . . . . .33

Fig 24. IDD with respect to VDD . . . . . . . . . . . . . . . . . . . .36

Fig 25. IDD(LCD) with respect to VLCD . . . . . . . . . . . . . . . .37

Fig 26. Typical clock frequency (fclk) with respect

to VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Fig 27. Frame frequency variation . . . . . . . . . . . . . . . . . .39

Fig 28. Driver timing waveforms . . . . . . . . . . . . . . . . . . .40

Fig 29. I2C-bus timing waveforms when SDA and

SDAACK are connected . . . . . . . . . . . . . . . . . . .40

Fig 30. Values for RPU(max). . . . . . . . . . . . . . . . . . . . . . . .42

Fig 31. Values for RPU(min) . . . . . . . . . . . . . . . . . . . . . . . .42

Fig 32. Operating range of the PCA85132 with respect

to the ITO track resistance. . . . . . . . . . . . . . . . . .43

Fig 33. SDA, SDAACK configurations . . . . . . . . . . . . . . .44

Fig 34. Cascaded configuration with two PCA85132

using the internal clock of the master . . . . . . . . .46

Fig 35. Cascaded configuration with one PCA85132

and one PCA85133 using the internal clock of

the master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Fig 36. Synchronization of the cascade for the various

PCA85132 drive modes . . . . . . . . . . . . . . . . . . . .48

Fig 37. Bare die outline of PCA85132 . . . . . . . . . . . . . . .49

Fig 38. Alignment marks . . . . . . . . . . . . . . . . . . . . . . . . .53

Fig 39. Tray details . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Fig 40. Tray alignment . . . . . . . . . . . . . . . . . . . . . . . . . . .55

PCA85132

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 9 April 2015

© NXP Semiconductors N.V. 2015. All rights reserved.

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