PCA9536 查看數據表（PDF） - NXP Semiconductors.
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PCA9536 Datasheet PDF : 24 Pages
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NXP Semiconductors
PCA9536
4-bit I2C-bus and SMBus I/O port
10. Dynamic characteristics
Table 11. Dynamic characteristics
Symbol Parameter
Conditions
fSCL
SCL clock frequency
tBUF
bus free time between a STOP and
START condition
tHD;STA
tSU;STA
hold time (repeated) START condition
set-up time for a repeated START
condition
tSU;STO
tHD;DAT
tVD;ACK
tVD;DAT
tSU;DAT
tLOW
tHIGH
tr
tf
tSP
set-up time for STOP condition
data hold time
data valid acknowledge time
data valid time
data set-up time
LOW period of the SCL clock
HIGH period of the SCL clock
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
pulse width of spikes that must be
suppressed by the input filter
Port timing
tv(Q)
tsu(D)
th(D)
data output valid time
data input set-up time
data input hold time
Standard-mode
I2C-bus
Min Max
0
100
4.7
-
Fast-mode I2C-bus Unit
Min
Max
0
400 kHz
1.3
- s
4.0
-
0.6
- s
4.7
-
0.6
- s
4.0
0
[1] 0.3
[2] 300
250
4.7
4.0
-
-
-
-
-
3.45
-
-
-
-
1000
300
50
0.6
0
0.1
50
100
1.3
0.6
20 + 0.1Cb[3]
20 + 0.1Cb[3]
-
- s
- s
0.9 s
- ns
- ns
- s
- s
300 ns
300 ns
50 ns
-
200
-
200 ns
100
-
100
- ns
1
-
1
- s
[1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] tVD;DAT = minimum time for SDA data output to be valid following SCL LOW.
[3] Cb = total capacitance of one bus line in pF.
SDA
tBUF
SCL
tr
tLOW
tHD;STA
P
S
tHD;DAT
tf
tHIGH
tSU;DAT
tHD;STA
tSU;STA
Sr
Fig 12. Definition of timing
PCA9536
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 7 November 2017
tSP
tSU;STO
0.7 × VDD
0.3 × VDD
0.7 × VDD
0.3 × VDD
P
002aaa986
© NXP Semiconductors N.V. 2017. All rights reserved.
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