PCA9536D 查看數據表（PDF） - NXP Semiconductors.

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PCA9536D

4-bit I2C-bus and SMBus I/O port

NXP Semiconductors. 

NXP Semiconductors

PCA9536

4-bit I2C-bus and SMBus I/O port

protocol

START

condition

(S)

bit 7

MSB

(A7)

bit 6

(A6)

bit 0

(R/W)

acknowledge

(A)

STOP

condition

(P)

tSU;STA

SCL

tBUF

SDA

tLOW tHIGH

1 / fSCL

tr

tf

tHD;STA

tSU;DAT tHD;DAT

Rise and fall times refer to VIL and VIH

Fig 13. I2C-bus timing diagram

tVD;DAT

0.7 × VDD

0.3 × VDD

tVD;ACK tSU;STO

0.7 × VDD

0.3 × VDD

002aab175

11. Test information

PULSE

GENERATOR

VDD

VI

VO

DUT

RT

RL

500 Ω

VDD

open

VSS

CL

50 pF

002aab880

RL = load resistor.

CL = load capacitance includes jig and probe capacitance.

RT = termination resistance should be equal to the output impedance Zo of the pulse generators.

Fig 14. Test circuitry for switching times

from output

under test

Fig 15. Test circuit

Table 12. Test data

Test

tv(Q)

Load

CL

50 pF

500 Ω

CL

50 pF

500 Ω

S1

2VDD

open

VSS

002aab881

RL

500 

Switch

2VDD

PCA9536

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6 — 7 November 2017

© NXP Semiconductors N.V. 2017. All rights reserved.

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