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PCA9539BS

16-bit I2C-bus and SMBus low power I/O port with interrupt and reset

NXP Semiconductors. 

NXP Semiconductors

PCA9539; PCA9539R

16-bit I2C-bus and SMBus low power I/O port with interrupt and reset

[3] The total current sourced by all I/Os must be limited to 160 mA (80 mA for IO0_0 through IO0_7 and 80 mA for IO1_0 through IO1_7).

11. Dynamic characteristics

Table 15. Dynamic characteristics

Symbol Parameter

fSCL

SCL clock frequency

tBUF

bus free time between a STOP and

START condition

tHD;STA

tSU;STA

hold time (repeated) START condition

set-up time for a repeated START

condition

tSU;STO

tVD;ACK

tHD;DAT

tVD;DAT

tSU;DAT

tLOW

tHIGH

tf

tr

tSP

set-up time for STOP condition

data valid acknowledge time

data hold time

data valid time

data set-up time

LOW period of the SCL clock

HIGH period of the SCL clock

fall time of both SDA and SCL signals

rise time of both SDA and SCL signals

pulse width of spikes that must be

suppressed by the input filter

Port timing

tv(Q)

data output valid time

tsu(D)

data input set-up time

th(D)

data input hold time

Interrupt timing

tv(INT_N) valid time on pin INT

trst(INT_N) reset time on pin INT

RESET timing

tw(rst)

trec(rst)

trst

reset pulse width

reset recovery time

reset time

Conditions

Standard-mode

I2C-bus

Min

Max

0

100

4.7

-

4.0

-

4.7

-

4.0

[1] 0.3

0

[2] 300

250

4.7

4.0

[3]

-

[3]

-

-

-

3.45

-

-

-

-

-

300

1000

50

[4]

-

200

150

-

1

-

-

4

-

4

4

-

0

-

[5][6] 400

-

Fast-mode I2C-bus Unit

Min

Max

0

400 kHz

1.3

- µs

0.6

- µs

0.6

- µs

0.6

0.1

0

50

100

1.3

0.6

20 + 0.1Cb

20 + 0.1Cb

-

- µs

0.9 µs

- ns

- ns

- ns

- µs

- µs

300 ns

300 ns

50 ns

-

200 ns

150

- ns

1

- µs

-

4 µs

-

4 µs

4

- ns

0

- ns

400

- ns

[1] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW.

[2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.

[3] Cb = total capacitance of one bus line in pF.

[4] tv(Q) measured from 0.7VDD on SCL to 50 % I/O output.

[5] Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions.

[6] Upon reset, the full delay will be the sum of trst and the RC time constant of the SDA bus.

PCA9539_PCA9539R_5

Product data sheet

Rev. 05 — 28 July 2008

© NXP B.V. 2008. All rights reserved.

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