PCA9554C 查看數據表（PDF） - NXP Semiconductors.

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PCA9554C

Low-voltage 8-bit I2C-bus and SMBus low power I/O port with interrupt, weak pull-up

NXP Semiconductors. 

NXP Semiconductors

PCA9554B; PCA9554C

Low-voltage 8-bit I2C-bus/SMBus low power I/O port

VDD

3.3 V

5V

VDD

Pn

LED

100 kΩ

VDD

LED

Pn

002aag164

Fig 12. High value resistor in parallel with

the LED

002aag165

Fig 13. Device supplied by a lower voltage

8.2 Power-on reset requirements

In the event of a glitch or data corruption, PCA9554B/PCA9554C can be reset to its

default conditions by using the power-on reset feature. Power-on reset requires that the

device go through a power cycle to be completely reset. This reset also happens when the

device is powered on for the first time in an application.

The two types of power-on reset are shown in Figure 14 and Figure 15.

VDD

ramp-up

ramp-down

td(rst)

re-ramp-up

(dV/dt)r

(dV/dt)f

time to re-ramp

when VDD drops

below 0.2 V or to VSS

(dV/dt)r

Fig 14. VDD is lowered below 0.2 V or 0 V and then ramped up to VDD

time

002aah329

VDD

ramp-down

ramp-up

VI drops below POR levels

(dV/dt)f

td(rst)

time to re-ramp

when VDD drops

to VPOR(min) − 50 mV

(dV/dt)r

time

002aah330

Fig 15. VDD is lowered below the POR threshold, then ramped back up to VDD

Table 10 specifies the performance of the power-on reset feature for

PCA9554B/PCA9554C for both types of power-on reset.

PCA9554B_PCA9554C

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 19 September 2012

© NXP B.V. 2012. All rights reserved.

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