PCA9555A 查看數據表（PDF） - NXP Semiconductors.
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PCA9555A Datasheet PDF : 39 Pages
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NXP Semiconductors
PCA9555A
Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
Table 13. Recommended supply sequencing and ramp rates
Tamb = 25 C (unless otherwise noted). Not tested; specified by design.
Symbol Parameter
Condition
Min Typ Max Unit
(dV/dt)f fall rate of change of voltage
Figure 15
0.1
-
(dV/dt)r rise rate of change of voltage
Figure 15
0.1
-
td(rst)
reset delay time
Figure 15; re-ramp time when
1
-
VDD drops below 0.2 V or to VSS
Figure 16; re-ramp time when
1
-
VDD drops to VPOR(min) 50 mV
VDD(gl) glitch supply voltage difference
Figure 17
[1] -
-
tw(gl)VDD supply voltage glitch pulse width Figure 17
[2] -
-
VPOR(trip) power-on reset trip voltage
falling VDD
0.7
-
rising VDD
-
-
2000 ms
2000 ms
-
s
-
s
1
V
10
s
-
V
1.4
V
[1] Level that VDD can glitch down to with a ramp rate of 0.4 s/V, but not cause a functional disruption when tw(gl)VDD < 1 s.
[2] Glitch width that will not cause a functional disruption when VDD(gl) = 0.5 VDD.
Glitches in the power supply can also affect the power-on reset performance of this
device. The glitch width (tw(gl)VDD) and glitch height (VDD(gl)) are dependent on each
other. The bypass capacitance, source impedance, and device impedance are factors that
affect power-on reset performance. Figure 17 and Table 13 provide more information on
how to measure these specifications.
VDD
∆VDD(gl)
tw(gl)VDD
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Fig 17. Glitch width and glitch height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition
is released and all the registers and the I2C-bus/SMBus state machine are initialized to
their default states. The value of VPOR differs based on the VDD being lowered to or from
0 V. Figure 18 and Table 13 provide more details on this specification.
VDD
VPOR (rising VDD)
VPOR (falling VDD)
time
POR
PCA9555A
Product data sheet
Fig 18. Power-on reset voltage (VPOR)
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 11 September 2012
time
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© NXP B.V. 2012. All rights reserved.
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