EM78R911 查看數據表（PDF） - ELAN Microelectronics

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EM78R911

8-bit micro-controller

ELAN Microelectronics 

EM78911

8-bit micro-controller

VII.6 Interrupt

The CALLER ID IC has internal interrupts which are falling edge triggered, as followed : TCC timer overflow

interrupt (internal) , two 8-bit counters overflow interrupt .

If these interrupt sources change signal from high to low , then RF register will generate '1' flag to

corresponding register if you enable IOCF register.

RF is the interrupt status register which records the interrupt request in flag bit. IOCF is the interrupt mask

register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the

interrupts (when enabled) generated, will cause the next instruction to be fetched from address 008H. Once in the

interrupt service routine the source of the interrupt can be determined by polling the flag bits in the RF register. The

interrupt flag bit must be cleared in software before leaving the interrupt service routine and enabling interrupts to

avoid recursive interrupts.

There are four external interrupt pins including INT0 , INT1 , INT2 , INT3 . And four internal interrupt

available.

Internal signals include TCC,CNT1,CNT2,FSK and CALL WAITING data. The last two will generate a

interrupt when the data trasient from high to low.

External interrupt INT0 , INT1 , INT2 , INT3 signals are from PORT7 bit0 to bit3 . If IOCF is enable then

these signal will cause interrupt , or these signals will be treated as general input data .

After reset, the next instruction will be fetched from address 000H and the instruction inturrept is 001H and the

hardware inturrept is 008H.

TCC will go to address 0x08 in GREEN mode or NORMAL mode after time out. And it will run next

instruction from “SLEP” instruction. These two cases will set a RF flag.

It is very important to save ACC,R3 and R5 when processing a interruption.

Address

Instruction

Note

0x08

DISI

;Disable interrupt

0x09

MOV A_BUFFER,A ;Save ACC

0x0A

SWAP A_BUFFER

0x0B

SWAPA 0x03

;Save R3 status

0x0C

MOV R3_BUFFER,A

0x0D

MOV A,0x05

;Save ROM page register

0x0E

MOV R5_BUFFER,A

:

:

:

:

:

MOV A,R5_BUFFER ;Return R5

:

MOV 0X05,A

:

SWAPA R3_BUFFER ;Return R3

:

MOV 0X03,A

:

SWAPA A_BUFFER ;Return ACC

:

RETI

VII.7 Instruction Set

Instruction set has the following features:

(1). Every bit of any register can be set, cleared, or tested directly.

(2). The I/O register can be regarded as general register. That is, the same instruction can operates on I/O register.

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