M68HC11KA 查看數據表（PDF） - Motorola => Freescale
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M68HC11KA Datasheet PDF : 68 Pages
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PWCLK —Pulse-Width Modulation Clock Select
$0060
Bit 7
6
5
4
3
2
1
Bit 0
CON34 CON12 PCKA2 PCKA1
—
PCKB3 PCKB2 PCKB1
RESET:
0
0
0
0
0
0
0
0
CON34 —Concatenate Channels 3 and 4
Channel 3 is high-order byte, and channel 4 (port H, bit 3) is output. Clock source is determined by
PCLK4.
0 = Channels 3 and 4 are separate 8-bit PWMs.
1 = Channels 3 and 4 are concatenated to create one 16-bit PWM channel.
CON12 —Concatenate Channels One and Two
Channel 1 is high order byte, and channel 2 (port H, bit 1) is output. Clock source is determined by
PCLK2.
0 = Channels 1 and 2 are separate 8-bit PWMs
1 = Channels 1 and 2 are concatenated to create one 16-bit PWM channel.
PCKA[2:1] —Prescaler for Clock A (See also PWSCAL register)
Determines the rate of clock A
PCKA[2:1]
00
01
10
11
Value of Clock A
E
E/2
E/4
E/8
Bit 3 — Not implemented
Always reads zero
PCKB[3:1] — Prescaler for Clock B
Determines the rate for clock B
PCKB[3:1]
000
001
010
011
100
101
110
111
Value of Clock B
E
E/2
E/4
E/8
E/16
E/32
E/64
E/128
MOTOROLA
64
MC68HC11KA4
MC68HC11KA4TS/D
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