DAC-8841GBC 查看數據表（PDF） - Analog Devices
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DAC-8841GBC Datasheet PDF : 11 Pages
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DAC-8841 -SPECIFICATIONS
ELECTRICAL CHARACTERISTICS: VoD = +5 V, All V,nX = +1.5 V, VrefL = OV, = -AO^C to +85®C apply for DAC-
8841 F, unless otherwise noted.
Parameter
Symbol Conditions
Min Typ Max Units
STATIC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Half-Scale Output Voltage
Zero-Scale Output Voltage
Output Voltage Drift
N
INL
DNL
Vhs
Vzs
TCVhs
All Specifications Apply for DACs A, B, C,
D, E, F, G, H
Note 1
All Devices Monotonic, Note 1
PR = 0 V, Sets D = 80h
Digital Code = OOh
PR = 0 V, Sets D = SOh
1.475
±1/2
1.500
20
10
±1.5
±1
1.525
100
Bits
LSB
LSB
V
mV
iivrc
SIGNAL INPUTS
Appliesto All Inputs Vn^X or V^EpL
Input Voltage Range
Input Resistance
Input Capacitance
REF Low Resistance
REF Low Capacitance
E DAC OUTPUTS
Voltage Range
Output Current
Capadtive Load
T DYNAMIC PERFORMANCE
Multiplying Gain Bandwidth
Slew Rate
E Total Harmonic Distortion
IVR
Rin
On
RrefL
CrefL
OVR
Iqut
GBW
+SR
-SR
THD
L Spot Noise Voltage
Output Settling Time
Channel to Channel Crosstalk
Ct
Digital Feedthrough
Q
O POWER SUPPLIES
Positive Supply Current
Idd
Power Dissipation
Pdiss
DC Power Supply Rejection Ratio PSRR
S Power Supply Range
PSR
DIGITAL INPUTS
Logic High
VlH
Logic Low
Vn,
B Input Current
II
Input Capacitance
Ql
Input Coding
DIGITAL OUTPUT
O Logic High
Vqh
0
D = 55h; Code Dependent
4
Code Dependent
D = ABh; Code Dependent
0.3
Code Dependent
Applies to All Outputs VqutX
Rl = 10 kft
0
AVout < 25mV, Vn^X = I.375V, PR = 0 V
±5
No Oscillation
Applies to All DACs
VinX = 100mV p-p +1.0 V dc
1
Measured 10% to 90%
AVoutX = +3 V
1.3
AVoutX = -3 V
1.3
VinX = 1 V p-p + 1.0 V dc, D = FFh, f = 1 kHz,
fu = 80 kHz
f = IkHz
±1 LSB Error Band, Sjq to 255io
Measured Between Adjacent Channels, f = 100 kHz 60
VrefL = +1.5 V, D = 0 to FFh
PR = OV
PR = OV
Vdd
4.75
2.4
loH = -0-4 mA
3.5
1.5
10
19
30
0.75
190 250
3
200
2.5
4.0
2.5
0.01
0.17
3.5 6
70
6
19
95
5.00
26
130
0.01
5.25
0.8
±10
8
Binary
Logic Low
Vol.
Uj = 1.6 mA
0.4
V
kn
pF
kn
pF
V
mA
pF
MHz
V/p,s
V/|jis
%
p,V/VHz
|XS
dB
nVs
mA
mW
%/%
V
V
V
pA
pF
TIMING SPECIFICATIONS
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay
DAC Register Load Pulse Width
Preset Pulse Width
Clock Edge to Load Time
Load-Edge to Next Clock Edge
kw, kx
tos
^DH
tpD
^LD
tpR
tcKLD
^LDCK
80
ns
40
ns
20
ns
120 ns
70
ns
50
ns
30
ns
60
ns
^[NL^d DNL tests do not include operation at codes 0thru 7due to zero-scale output voltage. For bias voltages above 100 mV on VrhfL, INL and DNL are
maintained over all codes.
Specifications subjectto changewithout notice.
-2-
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