PEB20324 查看數據表（PDF） - Infineon Technologies

零件编号

产品描述 (功能)

生产厂家

PEB20324

Multichannel Network Interface Controller for HDLC + Extensions MUNICH128X

Infineon Technologies 

PEB 20324

PEF 20324

Pin Descriptions

Table 2-2

Pin No.

107

105

106

97

99

98

100

Pin Descriptions by Functional Block: Port 1 Serial Interface

Symbol Type Description

RxCLK1 I

Receive Clock 1

The clock input pin used for sampling the data on

RxD1 The MUNICH128X supports the following PCM

clock rates, programmed via the MODE1 register:

T1: 1.536 MHz, 1.544 MHz, 3.088 MHz, 6.176 MHz;

E1: 2.048 MHz, 4.096 MHz, 8.192 MHz.

RxD1

I

Receive Data 1

The data input pin which is sampled using RxCLK1.

RSP1

I

Receive Synchronization Pulse 1

The input pin used for Rx PCM frame synchronization;

the synchronization pulse marks the first bit in the

PCM frame.

TxCLK1 I

Transmit Clock 1

The clock input used for clocking out the data on

TxD1. In most applications, the signal that drives this

pin is externally connected to RxCLK1.

TxD1

O Transmit Data 1

Provides the data which is clocked out of the

MUNICH128X by TxCLK1; data is push-pull for active

bits in the PCM frame and TRISTATE™ for inactive

bits.

TSP1

I

Transmit Synchronization Pulse 1

The input pin used for Tx PCM frame synchronization;

the synchronization pulse marks the last bit in the

PCM frame.

TxDEN1 O

Transmit Data Enable 1

An active low output signal which specifies data on the

TxD1 output pin is valid.

Hardware Reference Manual

18

04.99

Share Link: