PIC16F627 查看數據表（PDF） - Microchip Technology

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PIC16F627

FLASH-Based 8-Bit CMOS Microcontroller

Microchip Technology 

PIC16F62X

3.2.2 SPECIAL FUNCTION REGISTERS

The SFRs are registers used by the CPU and Periph-

eral functions for controlling the desired operation of

the device (Table 3-1). These registers are static RAM.

The special registers can be classified into two sets

(core and peripheral). The SFRs associated with the

“core” functions are described in this section. Those

related to the operation of the peripheral features are

described in the section of that peripheral feature.

TABLE 3-1: SPECIAL REGISTERS SUMMARY BANK 0

Address Name Bit 7 Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR

Reset(1)

Bank 0

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

INDF

TMR0

PCL

STATUS

FSR

PORTA

PORTB

—

—

—

PCLATH

INTCON

PIR1

—

TMR1L

TMR1H

Addressing this location uses contents of FSR to address data memory (not a physical register)

Timer0 Module’s Register

Program Counter's (PC) Least Significant Byte

IRP

RP1

RP0

TO

PD

Z

DC

Indirect data memory address pointer

RA7

RA6

RA5

RA4

RA3

RA2

RA1

RB7

RB6

RB5

RB4

RB3

RB2

RB1

Unimplemented

Unimplemented

Unimplemented

—

—

—

Write buffer for upper 5 bits of program counter

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

EEIF

CMIF

RCIF

TXIF

—

CCP1IF TMR2IF

Unimplemented

Holding register for the Least Significant Byte of the 16-bit TMR1

Holding register for the Most Significant Byte of the 16-bit TMR1

C

RA0

RB0

RBIF

TMR1IF

xxxx xxxx

xxxx xxxx

0000 0000

0001 1xxx

xxxx xxxx

xxxx 0000

xxxx xxxx

—

—

—

---0 0000

0000 000x

0000 -000

—

xxxx xxxx

xxxx xxxx

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

Legend:

Note 1:

T1CON

—

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000

TMR2

TMR2 module’s register

0000 0000

T2CON

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000

—

Unimplemented

—

—

Unimplemented

—

CCPR1L Capture/Compare/PWM register (LSB)

xxxx xxxx

CCPR1H Capture/Compare/PWM register (MSB)

xxxx xxxx

CCP1CON —

—

CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000

RCSTA

SPEN

RX9

SREN

CREN

ADEN

FERR

OERR

RX9D 0000 -00x

TXREG USART Transmit data register

0000 0000

RCREG USART Receive data register

0000 0000

—

Unimplemented

—

—

Unimplemented

—

—

Unimplemented

—

—

Unimplemented

—

CMCON C2OUT C1OUT

C2INV

C1INV

CIS

CM2

CM1

CM0 0000 0000

— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

shaded = unimplemented

For the Initialization Condition for Registers Tables, refer to Table 14-7 and Table 14-8 on page 98.

Details

on Page

25

43

13

19

25

29

34

—

—

—

25

21

23

—

46

46

46

50

50

—

—

61

61

61

67

74

77

—

—

—

—

53

 2003 Microchip Technology Inc.

Preliminary

DS40300C-page 15

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