LTC1196/LTC1198
BLOCK DIAGRAM
VCC (VCC/VREF)
CS
(CS/SHUTDOWN) CLK
IN+ (CH0)
IN– (CH1)
BIAS AND
SHUTDOWN CIRCUIT
SERIAL PORT
CSMPL
–
SAR
+
HIGH SPEED
COMPARATOR
CAPACITIVE DAC
DOUT
PIN NAMES IN PARENTHESES
REFER TO THE LTC1198
GND
TEST CIRCUITS
On and Off Channel Leakage Current
5V
ION
A
ON CHANNEL
IOFF
A
POLARITY
••••
OFF
CHANNEL
1196/98 TC01
Voltage Waveform for DOUT Rise and Fall Times, tr, tf
DOUT
VOH
VOL
tr
tf
1196/98 TC04
12
VREF (DIN)
1196/98 BD
Load Circuit for tdDO, tr and tf
1.4V
DOUT
3k
100pF
TEST POINT
1196/98 TC02
Voltage Waveform for DOUT Delay Time, tdDO, thDO
CLK
DOUT
VIH
tdDO
thDO
VOH
VOL
1196/98 TC03
119698fa