PLL130-05QC 查看數據表（PDF） - PhaseLink Corporation
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PLL130-05QC Datasheet PDF : 4 Pages
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PLL130-05
High Speed Translator Buffer to PECL (Enable Low)
FEATURES
• Differential PECL output
• Single AC coupled input (min. 100mV swing).
• Input range from DC to 1.0 GHz.
• 2.5V to 3.3V operation.
• Available in 3x3mm QFN.
DESCRIPTION
PIN CONFIGURATION
(TOP VIEW)
GND
GND
GND
OEV
12
13
11 10
9
8
14
PLL130-05
7
15
6
16
5
123 4
PECL_BAR
VDD
PECL
GND
The PLL130-05 is a low cost, high performance,
high speed, buffer that reproduces any input fre-
quency from DC to 1.3GHz. It provides one pair
of differential PECL outputs. Any input signal
with at least 100mV swing can be used as refer-
ence signal. This chip is ideal for conversion
from sine wave, TTL, CMOS, or LVDS to PECL.
Note: V denotes internal pull down
BLOCK DIAGRAM
REF_IN
Input
Amplifier
PECL_BAR
PECL
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1
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