HI7188(2000) 查看數據表（PDF） - Intersil

零件编号

产品描述 (功能)

生产厂家

HI7188
(Rev.:2000)

8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System

Intersil 

HI7188

Functional Description

The HI7188 contains a differential 8 channel multiplexer,

Programmable Gain Instrumentation Amplifier (PGIA), 4th

order sigma-delta ADC, integrating filter, line noise rejection

filters, Calibration and data RAMs, bidirectional serial port,

clock oscillator, and a microsequencer. The 8 to 1

multiplexer at the input combined with the resetable

modulator on the HI7188 allow for conversions of up to 8

differential channels with each channel being updated at a

rate of 240 samples per second (with 60Hz line noise

rejection enabled). The device can be programmed for

conversion of any combination of physical channels. After

the signal has passed through the multiplexer, it moves into

the PGIA. The PGIA can be configured in gains of 1, 2, 4

and 8 specific for each of the 8 logical channels. The signal

then enters the sigma delta modulator. The patented one-

shot sigma delta modulator is a fourth order modulator which

converts the differential analog signal into a series of one bit

outputs. The 1’s density of this data stream provides a digital

representation of the analog input. The output of the

modulator is fed into the integrating low pass digital filter.

Data out of the filter is available after 201 bits are received

from the modulator.

If the device is in line noise rejection mode, the integrating

filter data is routed to the Line Noise Rejection filters. This

data is then calibrated using the offset and gain calibration

coefficients. Data coding is performed and the result is

stored in the data RAM. If line noise rejection is disabled, the

averaging filter is bypassed, calibration is performed on the

data from the integrating filter, the data is coded, and the

result is stored in the data RAM.

This data flow of modulation, filter and calibrate is repeated

for each of the active logical channels (up to 8). After all

active logical channels are converted the HI7188 generates

an active low interrupt, End Of Scan (EOS), that indicates all

logical channels have been updated and valid data is

available to be read from the data RAM.

Converted data is read via the HI7188 serial I/O port which

is compatible with most synchronous transfer formats

including both the Motorola SPI and Intel 8051 series SSR

protocols. All RAMs, including the Data RAM, are accessed

in a “burst” mode. That is, the data for all active logical

channels is accessed in a single read communication cycle.

Using the HI7188

This section describes how to use the device for a typical

application. This includes power supply considerations, initial

reset, calibration and conversion. Please refer to Figure 7.

The analog and digital supplies and grounds are separate

on the HI7188 to minimize digital noise coupling into the

analog circuitry. Nominal supply voltages are AVDD = +5V,

DVDD = +5V, and AVSS = -5V. If the same supply is used

for AVDD and DVDD it is imperative that the supply is

separately decoupled to the AVDD and DVDD pins on the

HI7188. Separate analog and digital ground planes should

be maintained on the system board and the grounds should

be tied together back at the power supply.

When the HI7188 is powered up it needs to be reset by pulling

the RST line low. This resets the internal registers as shown in

Table 1. This initial configuration defines the part for one

active logical channel (physical channel 1, address 000),

conversion mode, unipolar operation, gain of one, no line

noise rejection, offset binary coding, MSB first I/O bit order,

descending I/O byte order, and single line interface. After the

RST line returns high, the device immediately begins

converting as described above without any further instruction.

There is no correction for offset or gain errors on the

converted data at this time. To ensure maximum performance,

calibration should be done as defined in the operation mode

section.

TABLE 1. REGISTER RESET VALUES

REGISTER

VALUE (HEX)

Data Output Registers

XXXX (undefined)

Channel Configuration Register #2

00XXXXXX

Channel Configuration Register #1

XXXXXXXX

Control Register

0000

Offset Calibration Registers

000000

Positive Full Scale Calibration Registers 800000

Negative Full Scale Calibration Registers 800000

The reset configuration should be updated to reflect the

users system including chip level and channel level

programming.

1. Chip level refers to programming common to all channels

such as 50/60 Hertz Line Noise Rejection, number of

active channels, etc. and is detailed in the Control

Register (CR) section.

2. Channel level programming is custom for each channel

such as gain, physical input and mode as detailed in the

Channel Configuration Registers (CCR) section.

A calibration routine should be performed next to remove

system offset and full scale errors (see Calibration section).

The CCR is used to place each channel of the device in

several operational modes including Conversion, System

Offset Calibration, System Positive Full Scale Calibration

and System Negative Full Scale Calibration. Each channel

inputs should be connected and settled to the correct input

condition before the CCR is programmed for each calibration

point. After a complete system calibration is performed, the

desired analog input is applied and accurate data can be

read via the serial interface. The device should be recalibrated

when there is a change in the user configuration (i.e. gain,

unipolar/bipolar), supply voltage or ambient temperature.

10

Share Link: