PSD4256G6V 查看數據表（PDF） - STMicroelectronics

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PSD4256G6V

Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs

STMicroelectronics 

PSD4256G6V

Pin Name Pin Type

Description

PB0-PB7

61-68

I/O

CMOS

or

Open

Drain

These pins make up Port B. These port pins are configurable and can have the

following functions:

1. MCU I/O – standard output or input port.

2. CPLD Macrocell (McellB0-McellB7) outputs.

3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16

and above).

PC0-PC7

41-48

I/O

CMOS

These pins make up Port C. These port pins are configurable and can have the

following functions:

1. MCU I/O – standard output or input port.

2. External Chip Select (ECS0-ECS7) outputs.

3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16

and above).

PD0

I/O

PD0 pin of Port D. This port pin can be configured to have the following functions:

CMOS 1. ALE/AS input – latches address on ADIO0-ADIO15.

79

or

2. AS input – latches address on ADIO0-ADIO15 on the rising edge.

Open 3. MCU I/O – standard output or input port.

Drain 4. Transparent PLD input (can also be PLD input for address A16 and above).

PD1

I/O

PD1 pin of Port D. This port pin can be configured to have the following functions:

CMOS 1. MCU I/O – standard output or input port.

80

or

2. Transparent PLD input (can also be PLD input for address A16 and above).

Open 3. CLKIN – clock input to the CPLD Macrocells, the APD Unit’s Power-down counter,

Drain

and the CPLD AND Array.

PD2

I/O

PD2 pin of Port D. This port pin can be configured to have the following functions:

CMOS 1. MCU I/O – standard output or input port.

1

or

2. Transparent PLD input (can also be PLD input for address A16 and above).

Open

Drain

3. PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and

I/O. When High, the PSD memory blocks are disabled to conserve power. The falling

edge of this signal can be used to get the device out of Power-down mode.

PD3

2

I/O

CMOS

or

Open

PD3 pin of Port D. This port pin can be configured to have the following functions:

1. MCU I/O – standard output or input port.

2. Transparent PLD input (can also be PLD input for address A16 and above).

Drain 3. WRH – for 16-bit data bus, WRITE to high byte, active low.

PE0

71

I/O

CMOS

or

Open

Drain

PE0 pin of Port E. This port pin can be configured to have the following functions:

1. MCU I/O – standard output or input port.

2. Latched address output.

3. TMS Input for the JTAG Serial Interface.

PE1

72

I/O

CMOS

or

Open

Drain

PE1 pin of Port E. This port pin can be configured to have the following functions:

1. MCU I/O – standard output or input port.

2. Latched address output.

3. TCK Input for the JTAG Serial Interface.

PE2

73

I/O

CMOS

or

Open

PE2 pin of Port E. This port pin can be configured to have the following functions:

1. MCU I/O – standard output or input port.

2. Latched address output.

Drain 3. TDI input for the JTAG Serial Interface.

PE3

74

I/O

CMOS

or

Open

Drain

PE3 pin of Port E. This port pin can be configured to have the following functions:

1. MCU I/O – standard output or input port.

2. Latched address output.

3. TDO output for the JTAG Serial Interface.

13/100

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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