PSD813F1V-12JIT 查看數據表（PDF） - STMicroelectronics
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PSD813F1V-12JIT
STMicroelectronics
PSD813F1V-12JIT Datasheet PDF : 110 Pages
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PSD813F1V
PSD REGISTER DESCRIPTION AND ADDRESS OFFSET
Table 5 shows the offset addresses to the PSD
registers relative to the CSIOP base address. The
CSIOP space is the 256 bytes of address that is al-
located by the user to the internal PSD registers.
Table 6 provides brief descriptions of the registers
in CSIOP space. The following section gives a
more detailed description.
Table 5. I/O Port Latched Address Output Assignments
MCU(1)
Port A(2)
Port A (3:0)
Port A (7:4)
Port B(2)
Port B (3:0)
Port B (7:4)
8051XA (8-bit)
N/A
Address a7-a4
Address a11-a8
N/A
80C251 (page mode)
N/A
N/A
Address a11-a8
Address a15-a12
All other 8-bit multiplexed
Address a3-a0
Address a7-a4
Address a3-a0
Address a7-a4
8-bit non-multiplexed bus
N/A
N/A
Address a3-a0
Address a7-a4
Note: 1. See the section entitled I/O PORTS, page 52, on how to enable the Latched Address Output function.
2. N/A = Not Applicable
Table 6. Register Address Offset
Register Name
Port
A
Port Port Port
B
C
D
Data In
00
01
10
11
Control
02
03
Data Out
04
05
12
13
Direction
06
07
14
15
Drive Select
08
09
16
17
Input Macrocell
0A 0B 18
Enable Out
0C 0D 1A 1B
Output Macrocells
AB
20
20
Output Macrocells
BC
21
21
Mask Macrocells
AB
22
22
Mask Macrocells
BC
23
23
Primary Flash
Protection
Secondary Flash
memory
Protection
JTAG Enable
PMMR0
PMMR2
Page
VM
Note: 1. Other registers that are not part of the I/O ports.
Other(1)
Description
Reads Port pin as input, MCU I/O input mode
Selects mode between MCU I/O or Address Out
Stores data for output to Port pins, MCU I/O output
mode
Configures Port pin as input or output
Configures Port pins as either CMOS or Open Drain
on some pins, while selecting high slew rate on other
pins.
Reads Input Macrocells
Reads the status of the output enable to the I/O Port
driver
READ – reads output of macrocells AB
WRITE – loads macrocell flip-flops
READ – reads output of macrocells BC
WRITE – loads macrocell flip-flops
Blocks writing to the Output Macrocells AB
Blocks writing to the Output Macrocells BC
C0 Read only – Flash Sector Protection
C2
Read only – PSD Security and EEPROM Sector
Protection
C7 Enables JTAG Port
B0 Power Management Register 0
B4 Power Management Register 2
E0 Page Register
E2
Places PSD memory areas in Program and/or Data
space on an individual basis.
17/110
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