PSD835G2-70UIT 查看數據表（PDF） - STMicroelectronics

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PSD835G2-70UIT

Flash PSD, 3 V supply, for 8-bit MCUs 4 Mbit + 256 Kbit dual Flash memories and 64 Kbit SRAM

STMicroelectronics 

PSD835G2V

Description

Table 1. Pin description (for the TQFP80 package) (continued)

Pin name Pin

Type

Description

PA0

58

PA1

57

These pins make up Port A. These port pins are configurable and can have the

PA2

56

I/O following functions:

PA3

55

CMOS MCU I/O – write to or read from a standard output or input port.

PA4

54 or Open CPLD macrocell (McellA0-7) outputs.

PA5

53

Drain Inputs to the PLDs.

PA6

52

PA7

51

Latched, transparent or registered PLD input.

PB0

68

PB1

67

These pins make up Port B. These port pins are configurable and can have the

PB2

66

I/O following functions:

PB3

65

CMOS MCU I/O – write to or read from a standard output or input port.

PB4

64 or Open CPLD macrocell (McellB0-7) output.

PB5

63

Drain Inputs to the PLDs.

PB6

62

PB7

61

Latched, transparent or registered PLD input.

PC0

48

PC1

47

These pins make up Port C. These port pins are configurable and can have the

PC2

46

I/O following functions:

PC3

45

CMOS MCU I/O – write to or read from a standard output or input port.

PC4

44 or Open

PC5

43

Drain External Chip Select (ECS0-7) output.

PC6

42

Latched, transparent or registered PLD input.

PC7

41

PD0 pin of Port D. This port pin can be configured to have the following functions:

I/O ALE/AS input latches addresses on ADIO0-ADIO15 pins.

PD0

79

CMOS

or Open

AS input latches addresses on ADIO0-ADIO15 pins on the rising edge.

Drain Input to the PLDs.

Transparent PLD input.

PD1 pin of Port D. This port pin can be configured to have the following functions:

I/O MCU I/O – write to or read from a standard output or input port.

PD1

80

CMOS

or Open Input to the PLDs.

Drain CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down

counter, and the CPLD AND Array.

PD2 pin of Port D. This port pin can be configured to have the following functions:

I/O MCU I/O – write to or read from a standard output or input port.

PD2

1

CMOS Input to the PLDs.

or Open PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory

Drain and I/O. When High, the PSD memory blocks are disabled to conserve power.

The trailing edge of CSI can be used to get the PSD out of power-down mode.

I/O PD3 pin of Port D. This port pin can be configured to have the following functions:

PD3

2

CMOS

or Open

MCU I/O – write to or read from a standard output or input port.

Drain Input to the PLDs.

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