PSD835G2-70UIT 查看數據表（PDF） - STMicroelectronics

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PSD835G2-70UIT

Flash PSD, 3 V supply, for 8-bit MCUs 4 Mbit + 256 Kbit dual Flash memories and 64 Kbit SRAM

STMicroelectronics 

PSD835G2V

2

PSD architectural overview

PSD architectural overview

PSD devices contain several major functional blocks. Figure 2. on page 18 shows the

architecture of the PSD device family. The functions of each block are described briefly in

the following sections. Many of the blocks perform multiple functions and are user

configurable.

2.1

Memory

Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed

discussion can be found in Memory blocks on page 29.

The 4Mbit (512K x 8) Flash memory is the primary memory of the PSD. It is divided into 8

equally-sized sectors that are individually selectable.

The 256Kbit (32K x8) secondary Flash memory is divided into 4 equally-sized sectors. Each

sector is individually selectable.

The 64 Kbit SRAM is intended for use as a scratch-pad memory or as an extension to the

MCU SRAM. If an external battery is connected to Voltage Standby (VSTBY, PC2), data is

retained in the event of power failure.

Each sector of memory can be located in a different address space as defined by the user.

The access times for all memory types includes the address latching and DPLD decoding

time.

2.2

Page Register

The 8-bit Page Register expands the address range of the MCU by up to 256 times. The

paged address can be used as part of the address space to access external memory and

peripherals, or internal memory and I/O. The Page Register can also be used to change the

address mapping of sectors of the Flash memories into different memory spaces for IAP.

2.3

PLDs

The device contains two PLDs, the Decode PLD (DPLD) and the Complex PLD (CPLD), as

shown in Table 2, each optimized for a different function. The functional partitioning of the

PLDs reduces power consumption, optimizes cost/performance, and eases design entry.

The DPLD is used to decode addresses and to generate Sector Select signals for the PSD

internal memory and registers. The CPLD can implement user-defined logic functions. The

DPLD has combinatorial outputs. The CPLD has 16 Output Macrocells (OMC) and 8

combinatorial outputs. The PSD also has 24 Input Macrocells (IMC) that can be configured

as inputs to the PLDs. The PLDs receive their inputs from the PLD Input Bus and are

differentiated by their output destinations, number of product terms, and macrocells.

The PLDs consume minimal power by using Power-Management design techniques. The

speed and power consumption of the PLD is controlled by the Turbo bit in PMMR0 and other

bits in the PMMR2. These registers are set by the MCU at run-time. There is a slight penalty

to PLD propagation time when invoking the power management features.

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