PSD835G2-70UIT 查看數據表（PDF） - STMicroelectronics

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PSD835G2-70UIT

Flash PSD, 3 V supply, for 8-bit MCUs 4 Mbit + 256 Kbit dual Flash memories and 64 Kbit SRAM

STMicroelectronics 

PSD835G2V

PSD architectural overview

2.8

In-application re-programming (IAP)

The primary Flash memory can also be programmed in-system by the MCU executing the

programming algorithms out of the secondary memory, or SRAM. Since this is a sizable

separate block, the application can also continue to operate. The secondary memory can be

programmed the same way by executing out of the primary Flash memory. The PLD or other

PSD Configuration blocks can be programmed through the JTAG port or a device

programmer. Table 4 indicates which programming methods can program different

functional blocks of the PSD.

2.9

Power management unit (PMU)

The Power Management Unit (PMU) gives the user control of the power consumption on

selected functional blocks based on system requirements. The PMU includes an Automatic

Power-down (APD) Unit that turns off device functions during MCU inactivity. The APD Unit

has a Power-down mode that helps reduce power consumption.

The PSD also has some bits that are configured at run-time by the MCU to reduce power

consumption of the CPLD. The Turbo bit in PMMR0 can be reset to 0 and the CPLD latches

its outputs and goes to sleep until the next transition on its inputs.

Additionally, bits in PMMR2 can be set by the MCU to block signals from entering the CPLD

to reduce power consumption. Please see Power management on page 84 for more details.

Table 4. Methods of programming different functional blocks of the PSD

Functional Block

JTAG/ISP

Device Programmer

IAP

Primary Flash Memory

Yes

Yes

Yes

Secondary Flash Memory

Yes

Yes

Yes

PLD Array (DPLD and CPLD)

Yes

Yes

No

PSD Configuration

Yes

Yes

No

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