GS820V32Q 查看數據表（PDF） - Giga Semiconductor

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GS820V32Q

64K x 32 Burst

Giga Semiconductor 

GSI TECHNOLOGY

GS820V32Q/T

4/5/6, 2.5V I/O, 2.0mA

64K x 32 Burst

GS820V32Q/T

80-133MHz (P/L)

66MHz Flow-Thru

Cycle

Synchronous truth table

Address used CE1 CE2 CE3 ADSP ADSC ADV BWx

Deselect

none

HXXXLXX

Deselect

none

L LXXLXX

Deselect

none

L XHX L XX

Deselect

none

L LXLXXX

Deselect

none

L XH L XXX

Read, begin burst external L H L L X X X

Read, begin burst external L H L H L X H

Read, continue burst next

XXXHHLH

Read, continue burst next

HXXXHLH

Read, suspend burst current

XXXHHHH

Read, suspend burst current

HXXXHHH

Write, begin burst external L H L H L X L

Write, continue burst next

XXXHHL L

Write, continue burst next

HXXXHL L

Write, suspend burst current

XXXHHHL

Write, suspend burst current

HXXXHHL

Note:

1. X=don’t care, H=logic high, L=logic low

2. BWx is the logic function of GW, BWE, BW1, BW2, BW3, BW4. See Byte Write Function table for detail.

3. All inputs in the table must meet setup and hold on rising edge of CLK.

DQ Bus Control and Asynchronous OE

Cycle

OE

DQ

Read

L

Q

Read

H

Hi-Z

Write

X

Hi-Z; D

Deselect

X

Hi-Z

Note: On the write cycle that follows read cycle, OE need to be held high prior to the start of write cycle to tri-state DQ buss and allow data

input to SRAM.

Rev. 9/09/97

4/15

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