PSD913G3-C-15B81 查看數據表（PDF） - STMicroelectronics
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PSD913G3-C-15B81 Datasheet PDF : 91 Pages
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PSD935G2
7.0 PSD935G2
Register
Description and
Address Offset
PSD9XX Family
Table 6 shows the offset addresses to the PSD935G2 registers relative to the CSIOP base
address. The CSIOP space is the 256 bytes of address that is allocated by the user to the
internal PSD935G2 registers. Table 6 provides brief descriptions of the registers in CSIOP
space. For a more detailed description, refer to section 9.
Table 6. Register Address Offset
Register Name Port A Port B Port C Port D Port E Port F Port G Other*
Data In
00
01
10
11
30
40
41
Control
32
42
43
Data Out
04
05
14
15
34
44
45
Direction
06
07
16
17
36
46
47
Drive Select
08
09
18
19
38
Flash Protection
Flash Boot
Protection
PMMR0
PMMR2
Page
VM
Memory_ID0
Memory_ID1
49
C0
C2
B0
B4
E0
E2
F0
F1
Description
Reads Port pin as input,
MCU I/O input mode
Selects mode between
MCU I/O or Address Out
Stores data for output
to Port pins, MCU I/O
output mode
Configures Port pin as
input or output
Configures Port pins as
either CMOS or Open
Drain on some pins, while
selecting high slew rate
on other pins.
Read only – Flash Sector
Protection
Read only – PSD Security
and Flash Boot Sector
Protection
Power Management
Register 0
Power Management
Register 2
Page Register
Places PSD memory
areas in Program and/or
Data space on an
individual basis.
Read only – Flash and
SRAM size
Read only – Boot type
and size
11
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