PSD9342V10MT 查看數據表（PDF） - STMicroelectronics

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PSD9342V10MT

Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

STMicroelectronics 

PSD834F2V

Pin Name Pin Type

Description

PC5

PC5 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC5) output.

13

I/O 3. Input to the PLDs.

4. TDI input2 for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PC6

PC6 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC6) output.

12

I/O 3. Input to the PLDs.

4. TDO output2 for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PC7

PC7 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

11

I/O

2. CPLD macrocell (McellBC7) output.

3. Input to the PLDs.

4. DBE – active Low Data Byte Enable input from 68HC912 type MCUs.

This pin can be configured as a CMOS or Open Drain output.

PD0

PD0 pin of Port D. This port pin can be configured to have the following functions:

1. ALE/AS input latches address output from the MCU.

10

I/O 2. MCU I/O – write or read from a standard output or input port.

3. Input to the PLDs.

4. CPLD output (External Chip Select).

PD1

PD1 pin of Port D. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

9

I/O

2. Input to the PLDs.

3. CPLD output (External Chip Select).

4. CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter, and

the CPLD AND Array.

PD2

PD2 pin of Port D. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

8

I/O

2. Input to the PLDs.

3. CPLD output (External Chip Select).

4. PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and I/

O. When High, the PSD memory blocks are disabled to conserve power.

VCC

15, 38

Supply Voltage

GND

1, 16,

26

Ground pins

Note: 1. The pin numbers in this table are for the PLCC package only. See the package information, on page 83 onwards, for pin numbers

on other package types.

2. These functions can be multiplexed with other functions.

PSD REGISTER DESCRIPTION AND ADDRESS OFFSET

Table 6 shows the offset addresses to the PSD

registers relative to the CSIOP base address. The

CSIOP space is the 256 bytes of address that is al-

located by the user to the internal PSD registers.

Table 6 provides brief descriptions of the registers

in CSIOP space. The following section gives a

more detailed description.

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