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PSD9342V10JT 查看數據表(PDF) - STMicroelectronics

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PSD9342V10JT Datasheet PDF : 89 Pages
First Prev 81 82 83 84 85 86 87 88 89
Figure 46. ISC Timing
TCK
tISCCH
t ISCCL
t ISCPSU tISCPH
PSD834F2V
TDI/TMS
t ISCPZV
t ISCPCO
ISC OUTPUTS/TDO
tISCPVZ
ISC OUTPUTS/TDO
AI02865
Table 55. Power-down Timing
Symbol
Parameter
tLVDV
ALE Access Time from Power-down
tCLWH
Maximum Delay from APD Enable to
Internal PDN Valid Signal
Note: 1. tCLCL is the period of CLKIN (PD1).
Conditions
Using CLKIN
(PD1)
-10
-15
-20
Unit
Min Max Min Max Min Max
145
150
200 ns
15 * tCLCL1
µs
81/89

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