PT6520-H 查看數據表（PDF） - Princeton Technology

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PT6520-H

LCD Driver IC

Princeton Technology 

PT6520

READ/WRITE TIMING FOR THE 68-PORT MPU

(Ta=25℃, VDD=0V, VSS=-5V)

Parameter

Signal

Symbol

Condition

System cycle time

tCYC6

VSS=-5V

VSS=-3V

Address set-up time

A0, CS, R/W

tAW6

VSS=-5V

VSS=-3V

Address hold time

tAH6

VSS=-5V

VSS=-3V

Control pulse width

tDS6

VSS=-5V

VSS=-3V

Data set-up time

tDH6

VSS=-5V

VSS=-3V

Data hold time

D0~D7

tOH6

CL=100pF VSS=-5V

CL=100pF

VSS=-3V

RD access time

tACC6

CL=100pF VSS=-5V

CL=100pF

VSS=-3V

Enable disable time

READ

WRITE

VSS=-5V

E

tew

VSS=-3V

VSS=-5V

VSS=-3V

Note: tCYC6 indicates the cycle during which CS/E are high; it does not indicate are cycle of the E signal.

Min.

1000

2000

20

40

10

30

80

160

10

20

10

20

-

-

250

400

150

250

Typ. Max

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

- 60

- 120

- 200

- 400

-

-

-

-

-

-

-

-

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

CONTROL TIMING FOR 80-PORT/68-PORT MPU

(Ta=25℃, VDD=0V, VSS=-5V)

Parameter

Signal

Symbol

Condition

Reset time

RES

tR

VSS=-5V

VSS=-3V

Reset time

(68-Port)

RES

tR1

VSS=-5V

VSS=-3V

Reset time

(80-Port)

RES

tR2

VSS=-5V

VSS=-3V

Notes:

1. The input timing of the FR delay time is determined by the PT6520 (Slave)

2. The output timing of the FR delay time is determined by the PT6520 (Master)

Min. Typ. Max Unit

1

- 750 μs

1.5

- 1000 μs

1

-

-

μs

1.5

-

-

μs

1

-

-

μs

1.5

-

-

μs

V1.9

17

July 2010

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