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RC5052 查看數據表(PDF) - Fairchild Semiconductor

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RC5052 Datasheet PDF : 18 Pages
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RC5052
Test Parameters
PRODUCT SPECIFICATION
tR
10%
90%
2V
tF
90%
2V
HIDRV
10%
tDT
tDT
2V
2V
LODRV
Figure 3. Output Drive Timing Diagram
Application Information
The RC5052 Controller
The RC5052 is a programmable synchronous DC-DC con-
troller IC optimized for 12V main power. It may also be used
in a 5V main power circuit when the crowbar and additional
programmability of the RC5052 are desired. When designed
around the appropriate external components, the RC5052 can
be configured to deliver more than 16A of output current, as
appropriate for the Katmai and Coppermine and other pro-
cessors. The RC5052 functions as a fixed frequency PWM
step down regulator.
Main Control Loop
Refer to the RC5052 Block Diagram on page 1. The RC5052
implements “summing mode control”, which is different
from both classical voltage-mode and current-mode control.
It provides superior performance to either by allowing a large
converter bandwidth over a wide range of output loads.
The control loop of the regulator contains two main sections:
the analog control block and the digital control block. The
analog section consists of signal conditioning amplifiers
feeding into a comparator which provides the input to the
digital control block. The signal conditioning section accepts
input from the IFB (current feedback) and VFB (voltage
feedback) pins and sets up two controlling signal paths. The
first, the voltage control path, amplifies the difference between
the VFB signal and the reference voltage from the DAC and
presents the output to one of the summing amplifier inputs.
The second, current control path, takes the difference between
the IFB and SW pins when the high-side MOSFET is on,
reproducing the voltage across the MOSFET and thus the
input current; it presents the resulting signal to another input
of the summing amplifier. These two signals are then summed
together. This output is then presented to a comparator look-
ing at the oscillator ramp, which provides the main PWM
control signal to the digital control block.
The digital control block takes the analog comparator input
and the main clock signal from the oscillator to provide the
appropriate pulses to the HIDRV and LODRV output pins.
These two outputs control the external power MOSFETs.
There is an additional comparator in the analog control section
whose function is to set the point at which the RC5052 current
limit comparator disables the output drive signals to the external
power MOSFETs.
High Current Output Drivers
The RC5052 contains two identical high current output drivers
that utilize high speed bipolar transistors in a push-pull config-
uration. The drivers’ power and ground are separated from
the chip’s power and ground for switching noise immunity.
The high-side driver’s power supply pin, VCCQP, is supplied
from an external 12V source through a series resistor. The
resulting voltage is sufficient to provide the gate to source
drive to the external MOSFETs required in order to achieve a
low RDS,ON. The low-side driver’s power supply pin, VCCP,
is supplied from the same source as VCCQP. The VCCQP
pin should be run as a charge pump for +12V Main Power, as
shown in Figure 1.
Internal Voltage Reference
The reference included in the RC5052 is a precision band-gap
voltage reference. Its internal resistors are precisely trimmed
to provide a near zero temperature coefficient (TC). Based on
the reference is the output from an integrated 5-bit DAC. The
DAC monitors the 5 voltage identification pins, VID0-4. When
the VID4 pin is at logic HIGH, the DAC scales the reference
voltage from 2.0V to 3.5V in 100mV increments. When VID4
is pulled LOW, the DAC scales the reference from 1.30V to
2.05V in 50mV increments. All VID codes are available,
including those below 1.80V. The output voltage may be
changed while the converter is on by changing the VID
codes; however, it is necessary to do so in 1-bit steps, to
avoid triggering the overvoltage protection.
Power Good (PWRGD)
The RC5052 Power Good function is designed in accordance
with the Pentium II DC-DC converter specifications and
provides a continuous voltage monitor on the VFB pin. The
circuit compares the VFB signal to the VREF voltage and
outputs an active-low interrupt signal to the CPU should the
power supply voltage deviate more than ±12% of its nominal
setpoint. The output is guaranteed open-collector high when
the power supply voltage is within ±7% of its nominal setpoint.
12
REV. 1.3.2 8/27/01

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