HIP4080(1996) 查看數據表（PDF） - Intersil

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HIP4080
(Rev.:1996)

80V/2.5A Peak, High Frequency Full Bridge FET Driver

Intersil 

HIP4080

HIP4080 Power-up Application Information

The HIP4080 H-Bridge Driver IC requires external circuitry

to assure reliable start-up conditions of the upper drivers. If

not addressed in the application, the H-Bridge power MOS-

FETs may be exposed to shoot-through current, possibly

leading to MOSFET failure. Following the instructions below

will result in reliable start-up.

The HIP4080 does not have an input protocol like the

HIP4081 that keeps both lower power MOSFETs off other

than through the DIS pin. IN+ and IN- are inputs to a com-

parator that control the bridge in such a way that only one of

the lower power devices is on at a time, assuming DIS is low.

However, keeping both lower MOSFETs off can be accom-

plished by controlling the lower turn-on delay pin, LDEL,

while the chip is enabled, as shown in Figure 32. Pulling

LDEL to VDD will indefinitely delay the lower turn-on delays

through the input comparator and will keep the lower MOS-

FETs off. With the lower MOSFETs off and the chip enabled,

i.e. DIS = low, IN+ or IN- can be switched through a full

cycle, properly setting the upper driver outputs. Once this is

accomplished, LDEL is released to its normal operating

point. It is critical that IN+/IN- switch a full cycle while LDEL

is held high, to avoid shoot-through. This start-up procedure

can be initiated by the supply voltage and/or the chip enable

command by the circuit in Figure 32.

VDD

VDD

ENABLE

56K

2N3906

56K

8.2V

100K

100K

0.1µF

FIGURE 32.

VDD RDEL

RDEL

1 BHB

2 HEN

3 DIS

4 VSS

5 OUT

6 IN+

7 IN-

8 HDEL

9 LDEL

10 AHB

BHO 20

BHS 19

BLO 18

BLS 17

VDD 16

VCC 15

ALS 14

ALO 13

AHS 12

AHO 11

VDD

DIS

12V, FINAL VALUE

8.3V TO 9.1V (ASSUMING 5% ZENER TOLERANCE)

LDEL

t1 =10ms t2

5.1V

NOTES:

2. Between t1 and t2 the IN+ and IN- inputs must cause the OUT pin to go through one complete cycle (transition order is not important). If

the ENABLE pin is low after the under-voltage circuit is satisfied, the ENABLE pin will initiate the 10ms time delay during which the IN+

and IN- pins must cycle at least once.

3. Another product, HIP4080A, incorporates undervoltage circuitry which eliminates the need for the above power up circuitry.

FIGURE 33. TIMING DIAGRAM FOR FIGURE 32

13

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