S24C01A 查看數據表（PDF） - Seiko Instruments Inc

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S24C01A

CMOS 2-WIRE SERIAL EEPROM

Seiko Instruments Inc 

CMOS 2-WIRED SERIAL EEPROM

S-24C01A/02A/04A

Rev. 2.2_30

8. Address Increment Timing

The address increment timing is as follows. See Figures 15 and 16. During reading operation, the memory

address counter is automatically incremented at the falling edge of the SCL clock (the 8th read data is

output).

During writing operation, the memory address counter is also automatically incremented at the falling

edge of the SCL clock when the 8th bit write data is fetched.

SCL

8

9

1

8

9

SDA

R / W=1

ACK Output

D7 Output

D0 Output

Address Increment

Figure 15 Address Increment Timing During Reading

SCL

SDA

8

9

1

R / W=0

ACK Output D7 Input

8

9

D0 Input

ACK Output

Address Increment

Figure 16 Address Increment Timing During Writing

Purchase of I2C components of Seiko Instruments Inc. conveys a license under the Philips I2C

Patent Rights to use these components in an I2C system, provided that the system conforms to the

I2C Standard Specification as defined by Philips.

Please note that any product or system incorporating this IC may infringe upon the Philips I2C Bus

Patent Rights depending upon its configuration.

In the event that such product or system incorporating the I2C Bus infringes upon the Philips Patent

Rights, Seiko Instruments Inc. shall not bear any responsibility for any matters with regard to and

arising from such patent infringement.

14

Seiko Instruments Inc.

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