S-25C080A 查看數據表（PDF） - Seiko Instruments Inc
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S-25C080A Datasheet PDF : 39 Pages
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CMOS SPI 8K SERIAL E2PROM
S-25C080A
Rev.1.1_00
Protect Operation
Table 17 shows the block settings of Write protect. Table 18 shows the protect operation for the device. As long as bit
SRWD, the Status Register Write Disable bit, in the status register is reset to “0” (it is in reset before the shipment), the
value of status register can be changed.
These are two statues when bit SRWD is set to “1”.
• Write in the status register is possible; Write protect ( WP ) is in “H”.
• Write in the status register is impossible; Write protect ( WP ) is in “L”. Therefore the Write protect area which is set
by protect bit (BP1, BP0) in the status register cannot be changed.
These operations are to set Hardware Protect (HPM).
• After setting bit SRWD, set Write protect ( WP ) to “L”.
• Set bit SRWD completed setting Write protect ( WP ) to “L”.
Figure 9 and 10 show the Valid timing in Write protect and Invalid timing in Write protect during the cycle Write to the
status register.
By inputting “H” to Write protect ( WP ), Hardware Protect (HPM) is released. If the Write protect ( WP ) is “H”,
Hardware Protect (HPM) does not function, Software Protect (SPM) which is set by the protect bits in the status
register (BP1, BP0) only works.
Table 17 The block settings of Write protect
Status register
BP1
BP0
The area of Write protect
Address of Write protect block
0
0
0%
None
0
1
25 %
300h to 3FFh
1
0
50 %
200h to 3FFh
1
1
100 %
000h to 3FFh
Table 18 Protect operation
Mode
WP pin Bit SRWD Bit WEL Write protect block General block
Status register
1
X
0
Write disable
Write disable
Write disable
Software Protect
1
X
1
Write disable
Write enable
Write enable
(SPM)
X
0
0
Write disable
Write disable
Write disable
X
0
1
Write disable
Write enable
Write enable
Hardware Protect
0
1
0
Write disable
Write disable
Write disable
(HPM)
0
1
1
Write disable
Write enable
Write disable
Remark X = Don’t care
20
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