SDU1378-0C 查看數據表（PDF） - Seiko Epson Corp
零件编号
产品描述 (功能)
生产厂家
SDU1378-0C Datasheet PDF : 94 Pages
| |||
SPECIFICATIONS
VDD = 2.7 to 4.5 V, VSS = 0 V, Ta = –20 to 75˚C unless otherwise noted
Parameter
Supply voltage
Register data retention voltage
Input leakage current
Output leakage current
Operating supply current
Quiescent supply current
Oscillator frequency
External clock frequency
Oscillator feedback resistance
TTL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
CMOS
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
Open-drain
LOW-level output voltage
Schmitt-trigger
Rising-edge threshold voltage
Falling-edge threshold voltage
Symbol
VDD
VOH
ILI
ILO
Iopr
IQ
fOSC
fCL
Rf
Condition
VI = VDD. See note 5.
VI = VSS. See note 5.
VDD = 3.5 V. See note 4.
See note 4.
Sleep mode,
VOSC1 = VCS = VRD = VDD
Measured at crystal,
47.5% duty cycle.
See note 6.
Min.
2.7
2.0
—
—
—
—
—
1.0
1.0
0.7
Rating
Typ.
3.5
—
0.05
0.10
3.5
—
0.05
—
—
—
Max.
4.5
6.0
2.0
5.0
—
7.0
20.0
8.0
8.0
3.0
Unit
V
V
µA
µA
mA
µA
MHz
MHz
MΩ
VIHT
VILT
VOHT
VOLT
See note 1.
See note 1.
IOH = –3.0 mA. See note 1.
IOL = 3.0 mA. See note 1.
0.5 VDD
VSS
2.4
—
—
VDD
V
—
0.2 VDD
V
—
—
V
—
VSS + 0.4
V
VIHC
See note 2.
0.8 VDD
—
VDD
V
VILC
See note 2.
VSS
—
0.2 VDD
V
VOHC
IOH = –2.0 mA. See note 2. VDD – 0.4
—
—
V
VOLC
IOH = 1.6 mA. See note 2.
—
—
VSS + 0.4
V
VOLN
IOL = 6.0 mA.
—
—
VSS + 0.4
V
VT+
See note 3.
VT–
See note 3.
0.5 VDD
0.7 VDD
0.8 VDD
V
0.2 VDD
0.3 VDD
0.5 VDD
V
Notes
1. D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15, VRD, VWR and VCE are TTL-level inputs.
2. SEL1 is CMOS-level inputs. YD, XD0 to XD3, XSCL, LP, WF, YDIS are CMOS-level outputs.
3. RES is a Schmitt-trigger input. The pulsewidth on RES must be at least 200 µs. Note that pulses of more than a few seconds will
cause DC voltages to be applied to the LCD panel.
4. fOSC = 10 MHz, no load (no display memory), internal character generator, 256 × 200 pixel display. The operating supply current can
be reduced by approximately 1 mA by setting both CLO and the display OFF.
5. VD0 to VD7 and D0 to D7 have internal feedback circuits so that if the inputs become high-impedance, the input state immediately
prior to that is held. Because of the feedback circuit, input current flow occurs when the inputs are in an intermediate state.
6. Because the oscillator circuit input bias current is in the order of µA, design the printed circuit board so as to reduce leakage currents.
S1D13305 Series
EPSON
9
Technical Manual
Share Link: 