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SED1354F2A 查看數據表(PDF) - Seiko Epson Corp
零件编号
产品描述 (功能)
生产厂家
SED1354F2A
LCD Controller ICs
Seiko Epson Corp
SED1354F2A Datasheet PDF : 94 Pages
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SPECIFICATIONS
T
a
= –20 to 75
°
C
Signal Symbol
Parameter
V
DD
= 4.5 to 5.5V V
DD
= 2.7 to 4.5V
Unit Condition
Min. Max. Min. Max.
EXT
φ
0 t
C
Clock period
100
—
125
—
ns
VCE
t
W
VCE HIGH-level
pulsewidth
t
CE
VCE LOW-level
pulsewidth
t
C
– 50 — t
C
– 50 —
ns
2t
C
– 30 — 2t
C
– 30 —
ns
t
CYW
Write cycle time
3t
C
—
3t
C
—
ns
t
AHC
Address hold time from
falling edge of VCE
2t
C
– 30
—
2t
C
– 40
—
ns
VA0 to
VA15
t
ASC
t
CA
t
AS
Address setup time to
falling edge of VCE
Address hold time from
rising edge of VCE
Address setup time to
falling edge of VWR
t
C
– 70
0
0
— t
C
– 110 —
—
0
—
—
0
—
ns
ns
CL = 100
pF
ns
t
AH2
Address hold time from
rising edge of VWR
10
—
10
—
ns
t
WSC
Write setup time to
falling edge of VCE
t
C
– 80 — t
C
– 115 —
ns
VWR
t
WHC
Write hold time from
falling edge of VCE
2t
C
– 20 — 2t
C
– 20 —
ns
t
DSC
Data input setup time to
falling edge of VCE
t
C
– 85
— t
C
– 125 —
ns
VD0 to
VD7
t
DHC
Data input hold time
from falling edge of VCE
2t
C
– 30
—
2t
C
– 30
—
ns
t
DH2
Data hold time from
rising edge of VWR
5
50
5
50
ns
Note:
VD0 to VD7 are latching input/outputs. While the bus is high impedance, VD0 to VD7 retain the write data until the data read
from the memory is placed on the bus.
14
EPSON
S1D13305 Series
Technical Manual
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