S1R72U01 查看數據表（PDF） - Seiko Epson Corp
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S1R72U01 Datasheet PDF : 32 Pages
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6. Pin Functions
VBUS (UVDD3 system)
BGA QFP
Name
-
12 VBUSFLG
-
13 VBUSEN
PU: Pull-up I/Os are used.
I/O
RESET
IN(PU) -
OUT
Low
Pin description
USB power switch fault detection signal
1: Normal, 0: Error
CMOS Schmitt input
Use when external USB power switch is added.
Leave open when not used.
USB power switch control signal
Use when external USB power switch is added.
Leave open when not used.
Serial I/F (CVDD system): Main CPU
BGA QFP
Name
I/O
-
30 MISO
Tri
-
28 MOSI
IN
-
31 SS
IN
-
33 SCK
IN
-
25 SIO_READY
OUT
-
27 XIRQ_STATUS OUT
-
26 XIRQ_EVENT OUT
RESET
High
-
-
-
Low
High
High
Pin description
Serial data output
(Hi-z is output when the SS pin is set to High.)
Serial data input
Slave selection
(Can be used to control output from the MISO pin. If
Hi-z output is not required, fix this pin at Low.)
Serial clock (not used: fix at Low)
Communication ready notification pin
Refer to the S1R72U01 Technical Manual for detailed
instructions on using this pin. Leave open when not
used.
Status notification
Refer to the S1R72U01 Technical Manual for detailed
instructions on using this pin. Leave open when not
used.
Event read request
Refer to the S1R72U01 Technical Manual for detailed
instructions on using this pin. Leave open when not
used.
Serial I/F (UVDD3 system): History Display
BGA QFP
Name
I/O
RESET
-
15 SIN0
IN
-
-
14 SOUT0
OUT
High
Pin description
Asynchronous serial data IN
Serial data IN pin for history display. Refer to the
S1R72U01 Development Support Manual for
specifics of history display. Fix at High when not used.
Asynchronous serial data OUT
Serial data OUT pin for history display. Refer to the
S1R72U01 Development Support Manual for
specifics of history display. Leave open when not
used.
8
Seiko Epson Corporation
S1R72U01 Data Sheet
(Rev. 1.20)
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