S4242 查看數據表（PDF） - Summit Microelectronics
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S4242 Datasheet PDF : 16 Pages
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S4242/S42WD42/S4261/S42WD61
Watchdog Timer Operation
The S42WD42/S42WD61 has a watchdog timer with a
nominal timeout period of 1.6 seconds. Whenever the
watchdog times out it will generate a reset output on both
RESET# and RESET. The watchdog timer will reset to t0
whenever the S42WD42/S42WD61 issues an ACKnowl-
edge. Therefore, the host system will need to issue a start
condition, followed by a valid address and command. It
can be a normal command as in the sequence of reading
or writing to the memory, or it can be a dummy command
issued solely for the purpose of resetting the watchdog
timer. Refer to Figure 17 for detailed sequence of opera-
tions.
The watchdog timer will be held in the reset state during
power-on while VCC is less than VTRIP. Once VCC exceeds
VTRIP, the watchdog will continue to be held in a reset state
for the duration of tPURST. After tPURST, the timer will be
released and begin counting.
If either reset input is asserted the watchdog timer will be
reset and remain in the reset condition until either tPURST
has expired or the reset input is released, whichever is
longer.
If the watchdog times out and no action is taken by the
host, the S42xxx will drive the reset outputs active for the
duration of tPURST at which point it will release the outputs
and begin the watchdog timer again. Refer to Figure 18 for
detailed sequence of operations.
S
T
S
A
T
R
R
O
T1010x x x W
P
SCL and SDA Idle
A
C
K
ACK response from S42xxx
Resets The Watchdog Timer
RESET#
t0
t < 1.6sec
S
T
S
A
T
R
R
O
T1010x x x W
P
SCL and SDA Idle
A
C
K
tPURST
t > 1.6sec
t0
FIGURE 17. SEQUENCE ONE
S
T
S
A
T
R
R
O
T1010x x x W
P
A
C
K
t0
2025 T fig17 2.0
S
T
S
A
T
R
R
O
T1010x x x W
P
SCL and SDA Idle
A
C
K
Watchdog Timer t0
RESET#
t > 1.6sec
SCL and SDA Idle
tPURST
t > 1.6sec
t0
FIGURE 18. SEQUENCE TWO
13
S
T
S
A
T
R
R
O
T1010x x x W
P
A
C
K
No Affect On tPURST
t0
2025 T fig18 2.0
2025 6.0 4/17/00
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