S5L9290X02
DIGITAL SIGNAL PROCESSOR FOR INTERNET AUDIO
$98 Command
Control cycle and gain control in CLV speed mode
Command
CLV gain
control
Address
10011000
($98)
D7
OVSPL
D6
WBN
D5
WPN
Data
D4
D3
D2
-
OVSPL
MS
WB
OVSPL (option)
Output by oversampling the CLV output (SMDP, SMDS) cycle by 7.35kHz *4
H : Over-sampling Enable,
L : Over-sampling Disable
WBN (option)
Bottom Hold Cycle control in the CLV speed mode
H : RFCK/64,
L : determined by WB
WPN (option)
Peak Hold cycle control in the CLV speed mode
H : RFCK/8,
L : determined by WP
OVSPL_MS (option)
SMDS output mode setting at over-sampling enable
H : PWM (H, L),
L : Tri-State (H, Hi-Z, L)
WB
Bottom Hold cycle control in the CLV speed mode
H : RFCK/16,
L : RFCK/32
WP
Peak Hold cycle control in the CLV speed mode
H : RFCK/2,
L : RFCK/4
(WPN, WP)
Control Cycle
(WBN, WB)
Control Cycle
00
RFCK/4
00
RFCK/32
01
RFCK/2
01
RFCK/16
10
RFCK/8
10
RFCK/64
11
RFCK/8
11
RFCK/64
GAIN
SMDS output gain control in the CLV speed mode
H : 0dB,
L : -12dB
D1
D0
WP
GAIN
20