S6B0721X11-XXX0 查看數據表（PDF） - Samsung

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S6B0721X11-XXX0

132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD

Samsung 

S6B0721

PRELIMINARY SPEC. VER. 0.1

132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD

FUNCTIONAL DESCRIPTION

MICROPROCESSOR INTERFACE

Chip Select Input

There are CS1B and CS2 pins for Chip Selection. The S6B0721 can interface with an MPU only when CS1B is “L”

and CS2 is “H”. When these pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled

and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the

counter are reset.

Parallel / Serial Interface

S6B0721 has three types of interface with an MPU, which are one serial and two parallel interfaces. This parallel

or serial interface is determined by PS pin as shown in table 8.

Table 8. Parallel / Serial Interface Mode

PS

Type

CS1B

CS2

H

Parallel

CS1B

CS2

L

Serial

CS1B

CS2

MI

Interface mode

H

6800-series MPU mode

L

8080-series MPU mode

*×

Serial-mode

*× : Don't care

Parallel Interface (PS = "H")

The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by MI as shown in

table 9. The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in table10.

Table 9. Microprocessor Selection for Parallel Interface

MI

CS1B

CS2

RS

E_RD RW_WR DB0 to DB7

MPU bus

H

CS1B

CS2

RS

E

RW

DB0 to DB7

6800-series

L

CS1B

CS2

RS

/RD

/WR

DB0 to DB7

8080-series

Common

RS

H

H

L

L

6800-series

E_RD

(E)

RW_WR

(RW)

H

H

H

L

H

H

H

L

Table 10. Parallel Data Transfer

8080-series

E_RD

(/RD)

RW_WR

(/WR)

L

H

H

L

L

H

H

L

Description

Display data read out

Display data write

Register status read

Writes to internal register (instruction)

13

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