SAA4700T_V5 查看數據表（PDF） - Philips Electronics

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SAA4700T_V5

VPS dataline processor

Philips Electronics 

Philips Semiconductors

VPS dataline processor

Preliminary specification

SAA4700T

SYMBOL

PARAMETER

CONDITIONS MIN.

SCL and SDA (pins 9 and 10)

VIL

VIH

II

CI

VO ACK

input voltage LOW

input voltage HIGH

input current

input capacitance

output voltage during acknowledge

on pin 10

−

3

0.9VP

−

−

IOL = 3 mA

−

tr

rise time

tf

fall time

tp L

pulse duration LOW

tp H

pulse duration HIGH

SCL

clock frequency

AD set input (pin 8)

−

−

4.7

4.0

−

note 2

VIL

input voltage LOW

VIH

input voltage HIGH

RESET input (pin 11)

address 23H

0

address 21H

2.4

note 2

VIL

input voltage LOW

VIH

input voltage HIGH

IIL

input current LOW

IIH

input current HIGH

reset active

−

reset non-active 2.4

−

−

Notes

1. With standard sync and data amplitude of 68% to 75% black-white.

2. If the open collector output DAV is used, a pull-up resistor to VP1 is necessary.

TYP.

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

0.01

MAX. UNIT

1.5

V

−

V

±10

µA

10

pF

0.4

V

1

µs

0.3

µs

−

µs

−

µs

100

kHz

0.4

V

VP

V

0.4

V

−

V

−10

µA

1

µA

March 1991

10

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