SAA4700T_V5 查看數據表（PDF） - Philips Electronics
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SAA4700T_V5 Datasheet PDF : 14 Pages
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Philips Semiconductors
VPS dataline processor
Preliminary specification
SAA4700T
FEATURES
• Adaptive sync slicer with buffered composite sync
output VCS
• Adaptive data slicer
• Data rate clock regenerator
• Field selection and line 16 decoding
• Startcode and biphase check
• Data valid output
• Storage of data line information in a 40 bit register bank
• I2C-bus transmission
GENERAL DESCRIPTION
The SAA4700T is a bipolar integrated circuit designed for
use in dataline receivers and incorporates a dataline slicer
and decoder. The slicer extracts the dataline signal from
the video signal and regenerates the data clock. It also
provides signals for the decoder in order to decode the
binary data that is transmitted in line 16 of every first field
of the composite video signal (video programming signal
and video recording programming by Teletext, VPS and
VPT systems). The decoded information out of words 5
and 11 to 14 is accessed via the built-in I2C-bus interface.
This information then can be used for programming a
video cassette recorder in order to start and stop a
recording of a television program at the correct aligned
time, regardless of a delay or extension in the transmission
time of the required program.
QUICK REFERENCE DATA
SYMBOL
VP
IP
Vi CVBS
Tamb
PARAMETER
supply voltage (pins 17 and 18)
total supply current
CVBS input signal sync-to-white
(peak-to-peak value)
operating ambient temperature
MIN.
4.5
−
0.5
TYP.
5
18
1
MAX.
5.5
23
1.4
UNIT
V
mA
V
0
−
+70
°C
ORDERING AND PACKAGE INFORMATION
EXTENDED
TYPE NUMBER
SAA4700T
20
PINS
Note
1. SOT163-1; 1996 November 13.
PACKAGE
PIN POSITION
mini-pack
MATERIAL
plastic
CODE
SOT163A (1)
March 1991
2
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