SAA4700T_V5 查看數據表（PDF） - Philips Electronics

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SAA4700T_V5

VPS dataline processor

Philips Electronics 

Philips Semiconductors

VPS dataline processor

Preliminary specification

SAA4700T

PINNING

SYMBOL PIN

DESCRIPTION

CVBS 1 video signal input (CVBS from TV)

SYNC 2 sync amplitude input (CVBS from TV)

GND1 3 analog ground (0 V)

GND2 4 digital ground (0 V)

Cblack

CSO

5 capacitor for black level

6 composite sync output

n.c.

7 not connected

AD

SCL

SDA

8 address set input

9 I2C-bus clock line

10 I2C-bus data line

RS

11 reset input active LOW

TP

12 test point for line 16 decoder

DAV

13 data available output active LOW

n.c.

14 not connected

Rosc

15 oscillator resistor for frequency

adjustment

CP

16 test point clock pulse

VP1

17 +5 V supply voltage (digital part)

VP2

18 +5 V supply voltage (analog part)

Cph

19 capacitor of phase detector

n.c.

20 not connected

PIN CONFIGURATION

handbook, halfpage

CVBS 1

20 n.c.

SYNC 2

19 Cph

GND1 3

18 VP2

GND2 4

17 VP1

Cblack 5

16 CP

SAA4700T

CSO 6

15 Rosc

n.c. 7

14 n.c.

AD 8

13 DAV

SCL 9

12 TP

SDA 10

11 RS

MBH797

Fig.2 Pin configuration.

External reset

The circuit provides an internal power-on reset. When

using this facility pin 11 should be connected to VP or, if

external reset (RESET = LOW) is to be used pin 11 should

be prepared by connecting pin 11 via a 10 kΩ pull-up

resistor to VP.

Reset forces the following:

• I2C-bus not to acknowledge

• DAV output to go HIGH (pin 13)

• I2C-bus transfer register to “FFF”

CVBS input

The CVBS signal is applied to the sync separator (pin 2)

via a decoupling capacitor and to the data slicer (pin 1) via

an RC high-pass filter. To enable proper storage of the

sync value in the decoupling capacitor, the sync generator

output resistance should not exceed 1 kΩ.

Black level

The capacitor connected to pin 5 stores the black level

value for the adaptive sync slicer.

March 1991

4

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