SAA7392 查看數據表（PDF） - Philips Electronics

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SAA7392

Channel encoder/decoder CDR60

Philips Electronics 

Philips Semiconductors

Channel encoder/decoder CDR60

7.5.2 MEAS1 PIN

The MEAS1 pin carries the 3 measurement signals: jitter

(sampled twice), PLL frequency, and asymmetry. Each

frame consists of 64 bits (each 4 system clock periods

long), beginning with a start bit, then data bits then pause

bits (see Fig.8). The start bit is always preceded by

17 pause bits; and the intermediate start bits at

locations 12, 24 and 36 guarantee that no other ‘1’ bit is

preceded by 17 ‘0’ bits, making the start detection easy.

The structure of the frame is described in Table 23 and

shown in Fig.8.

Table 23 Frame structure

BIT

0

1 to 10

11

12

13 to 22

23

24

25 to 32

33

34

37 to 46

47 to 63

VALUE

FUNCTION

logic 1

start bit

jitter<9:0> jitter word

logic 0

logic 1

intermediate start bit

pllfreq<9:0> PLL frequency word

logic 0

logic 1

intermediate start bit

assym<7:0> asymmetry word

logic 0

logic 1

intermediate start bit

jitter<9:0> second sample of jitter

word

logic 0

pause

handbook, halfpage

pause

bit 0 bit 1 bit 2 bit 3

start

bit

data bits

MGR798

Fig.8 Format on MEAS1 pin.

Preliminary specification

SAA7392

2000 Mar 21

21

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