Q67120-C0581 查看數據表（PDF） - Siemens AG

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Q67120-C0581

8-Bit CMOS Single-Chip Microcontroller Family

Siemens AG 

Memory Organization

3.4.2 Control of XRAM in the SAB 80C515A

There are two control bits in register SYSCON which control the use and the bus operation during

accesses to the additional On-Chip RAM in XDATA range (∧ XRAM).

Special Function Register SYSCON

MSB

LSB

Bit No.

7

6

5

4

3

2

1

0

Addr.0B1H –

–

–

–

–

– XMAP1 XMAP0 SYSCON

Bit

XMAP0

XMAP1

Function

Global enable/disable bit for XRAM memory.

XMAP0 = 0: The access to XRAM (= On-Chip XDATA memory) is enabled.

XMAP0 = 1: The access to RAM is disabled. All MOVX accesses are perfor-

med by the external bus. This bit is hardware protected.

Control bit for RD/WR signals during accesses to XRAM; this bit has no effect

if XRAM is disabled (XMAP0 = 1) or if addresses outside the XRAM address

range are used for MOVX accesses.

XMAP1 = 0: The signals RD and WR are not activated during accesses to

XRAM.

XMAP1 = 1: Ports 0, 2 and the signals RD and WR are activated during

accesses to XRAM.

Reset value of SYSCON is XXXX XX01B.

The control bit XMAP0 is a global enable/disable bit for the additional On-Chip RAM (XRAM). If this

bit is set, the XRAM is disabled, all MOVX accesses use external memory via the external bus. In

this case the SAB 80C515A can’t use the additional On-Chip RAM and is compatible with the types

without XRAM.

Semiconductor Group

3-14

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