SC1218 查看數據表（PDF） - Semtech Corporation

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SC1218

High Speed Synchronous MOSFET Driver

Semtech Corporation 

SC1218

POWER MANAGEMENT

Applications Information

THEORY OF OPERATION

The SC1218 is a high speed, robust, dual output driver

designed to drive top and bottom MOSFETs in a synchro-

nous Buck converter. It features internal bootstrap diode,

adaptive delay for shoot-through protection, 12V gate drive

voltage, and disable shutdown. It also supports dynamic

VID operation and CROWBAR function. This driver com-

bined with PWM controller SC2649 forms a multi-phase

voltage regulator for advanced microprocessors.

Startup and UVLO

To startup the driver, a supply voltage is applied to the VIN

pin of the SC1218. The top and bottom gates are held

low until VIN exceeds the UVLO threshold of the driver,

typically 4.0V. The UVLO threshold has hysteresis, typi-

cally -250mV, to improve the nosie immunity from the VIN

pin.

Gate Transition and Shoot-through Protection

Refer to the Timing Diagrams section, the rising edge of

the PWM input initiates the turn-off of bottom FET and the

turn-on of top FET. After a short propagation delay (tPDL_BG)

from PWM rising edge, the bottom gate falls (tF_BG). The

adaptive circuit in the SC1218 detects the bottom gate

voltage. It holds the top gate off until the bottom gate

voltage drops below 1.4V for a preset delay time (tPDH_TG).

This prevents the top FET from turning on until the bottom

FET is off. During the transition, the inductor current is

freewheeling through the body diode of either bottom FET

or top FET, depended on the direction of the inductor cur-

rent. The phase node could be low (ground) or high (VIN).

The falling edge of the PWM input controls the turn-off of

top FET and the turn-on of bottom FET. After a short

propagation delay (tPDL_TG) from PWM falling edge, the top

gate falls (t ). As the inductor current commutates from

F_TG

the top FET to the body diode of the bottom FET, the phase

node falls. The adaptive circuit in the SC1218 detects the

phase node voltage. It holds the bottom FET off until the

phase node voltage drops below 1.0V. This prevents the

top and bottom FETs from conducting simultaneously

(shoot-through). If the phase node voltage remains high

during the transition for a preset maximum BG turn on

delay (t

) , then the bottom gate will be turned on.

DH_MAX_BG

This supports the CROWBAR function and the sinking cur-

rent capacity required from dynamic VID operation.

narrow pulse for the driver. The pulse is so narrow that it

reaches the rising edge threshold of the SC1218 at one

point then immediately falls below the falling edge thresh-

old. To prevent the SC1218 from reacting to such narrow

PWM pulses, which may cause driver output ringing or

shoot through, advanced PWM timing circuitry is added to

ease the gate transitions. A minimum off-time (typically

140ns) for the bottom gate and a minimum on-time (typi-

cally 40ns) for the top gate are enforced to make the op-

eration safe under such conditions.

Dynamic VID Operation

Some processors changes VID dynamically during opera-

tion (Dynamic VID operation). A dynamic VID can occur

under light load or heavy load conditions. At light load, it

can force the converter to sink current. After turn-off of

the top FET, the reversed inductor current flows through

the body diode of the top FET instead of the bottom FET.

As a result, the phase node voltage remains high and voids

the adaptive circuit. SC1218 features a maximum BG

turn on delay (t

) to override the adaptive delay to

DH_MAX_BG

turn the bottom FET on. The preset maximum BG turn on

delay time (tDH_MAX_BG) from the PWM falling egde to the

bottom gate turn-on is set to be 175ns.

Switching Frequency, Inductor and MOSFETs

The SC1218 is capable of providing more than 3.5A peak

drive current, and operating up to 2MHz PWM frequency

without causing thermal stress on the driver. The selec-

tion of switching frequency, together with inductor and

FETs is a trade-off between the cost, size, and thermal

management of a multi-phase voltage regulator. Typically,

these parameters could be in the range of:

a) Switching Frequency: 100kHz to 500kHz per phase

b) Inductor Value: 0.2uH to 2uH

c) MOSFETs: 4mOhm to 20mOhm R and 20nC

DS(ON)

to 100nC total gate charge

Bootstrap and Chip Decoupling Capacitors

The top gate driver of the SC1218 is a DRN refered gate

drive whose supply voltage is derived from a bootstrap

circuit comprising a capacitor,CBST, and a built-in diode.

The capacitor value can be calculated based on the total

gate charge of the top FET, Q , and an allowed voltage

TOP

ripple on the capacitor, ∆VBST, in one PWM cycle:

Narrow PWM Pulse Filtering

During a load transient, soft start, or soft shutdown of the

voltage regulator, the PWM controller may generate a very

 2005 Semtech Corp.

9

CBST

>

QTOP

∆VBST

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