SC26C92 查看數據表（PDF） - Philips Electronics
零件编号
产品描述 (功能)
生产厂家
SC26C92 Datasheet PDF : 31 Pages
| |||
Philips Semiconductors
Dual universal asynchronous receiver/transmitter (DUART)
Product specification
SC26C92
AC CHARACTERISTICS1, 2, 4
VCC = 5V ± 10%, TA = –40_C to 85_C, unless otherwise specified.
SYMBOL
PARAMETER
LIMITS
Min
Typ3
Max
UNIT
Reset Timing (See Figure 3)
tRES
RESET pulse width
Bus Timing5 (See Figure 4)
200
ns
tAS
A0-A3 setup time to RDN, WRN Low
tAH
A0-A3 hold time from RDN, WRN Low
tCS
CEN setup time to RDN, WRN Low
tCH
CEN hold time from RDN, WRN High
tRW
WRN, RDN pulse width
tDD
Data valid after RDN Low
tDF
Data bus floating after RDN High
tDS
Data setup time before WRN or CEN High
tDH
Data hold time after WRN or CEN High
tRWD
High time between reads and/or writes5, 6
Port Timing5 (See Figure 5)
10
ns
25
ns
0
ns
0
ns
70
ns
55
ns
25
ns
25
ns
0
ns
30
ns
tPS
Port input setup time before RDN Low
tPH
Port input hold time after RDN High
tPD
OPn output valid from WRN High
Interrupt Timing (See Figure 6)
0
ns
0
ns
100
ns
INTRN (or OP3-OP7 when used as interrupts) negated from:
Read RxFIFO (RxRDY/FFULL interrupt)
Write TxFIFO (TxRDY interrupt)
tIR
Reset command (break change interrupt)
Stop C/T command (counter interrupt)
Read IPCR (input port change interrupt)
Write IMR (clear of interrupt mask bit)
100
ns
100
ns
100
ns
100
ns
100
ns
100
ns
Clock Timing (See Figure 7)
tCLK
fCLK
tCTC
fCTC
tRX
fRX
X1/CLK High or Low time
X1/CLK frequency
CTCLK (IP2) High or Low time
CTCLK (IP2) frequency
RxC High or Low time (16X)
RxC frequency (16X)
(1X)8
50
0.1 3.6864
8
55
0
8
30
0
16
0
1
ns
MHz
ns
MHz
ns
MHz
MHz
tTX
TxC High or Low time (16X)
fTX
TxC frequency (16X)
(1X)8
30
ns
0
16
MHz
0
1
MHz
Transmitter Timing (See Figure 8)
tTXD
TxD output delay from TxC external clock input on IP pin
tTCS
Output delay from TxC low at OP pin to TxD data output
Receiver Timing (See Figure 9)
60
ns
5
30
ns
tRXS
RxD data setup time before RxC high at external clock input on IP pin
50
ns
tRXH
RxD data hold time after RxC high at external clock input on IP pin
50
ns
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 3.0V with a transition time of 5ns
maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and
output voltages of 0.8V and 2.0V, as appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50pF, RL = 2.7KΩ to VCC.
5. Timing is illustrated and referenced to the WRN and RDN inputs. Also, CEN may be the ‘strobing’ input. CEN and RDN (also CEN and
WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.
6. If CEN is used as the ‘strobing’ input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must
be negated for tRWD to guarantee that any status register changes are valid.
7. Minimum frequencies are not tested but are guaranteed by design. Crystal frequencies 2 to 4 MHz.
8. Clocks for 1X mode should be symmetrical.
2000 Jan 31
7
Share Link: 