SC480 查看數據表（PDF） - Semtech Corporation

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SC480

Complete DDR1/2/3 Memory Power Supply

Semtech Corporation 

POWER MANAGEMENT

Pin Configuration

SC480 MLP24 Pin Out

PGND2 1

18 PGND1

VTTS 2

17 PGND1

VSSA 3

16 ILIM

T

TON 4

15 VDDP

REF 5

14 VDDP

VCCA 6

13 PGD

SC480

Ordering Information

Device(2)

Package(1)

SC480IMLTRT

MLPQ-24

SC480EVB

Evaluation Board

Notes:

1) Only available in tape and reel packaging. A reel contains 3000 devices.

2) This product is fully WEEE and RoHS compliant.

Pin Description

Pin #

1

2

3

4

Pin Name

PGND2

VTTS

VSSA

TON

Pin Function

Power ground for VTT output. Connect to thermal pad and ground plane.

Sense pin for VTT. Connect to VTT at the load.

Ground reference for analog circuitry. Connect to thermal pad.

This pin is used to sense VBAT through a pull-up resistor, RTON, which sets the top MOSFET

on-time. Bypass this pin with a 1nF capacitor to VSSA.

5

REF

Reference output. An internal resistor divider from VDDQS sets this voltage to 50% VDDQ (nomi-

nal). Bypass this pin with a series 10Ω/1μF to VSSA.

6

VCCA Analog supply voltage input. Use a 10Ω/1μF RC filter from +5V to VSSA.

7

NC

No Connect.

8

VDDQS Sense input for VDDQ. Used to set the on-time for the top MOSFET and also to set REF/VTT.

9

FB

Feedback select input for VDDQ. See FB Configuration Table.

10

VTTEN

Enable pin for VTT. Pull this pin low to disable VTT (REF remains present as long as VDDQ is

present).

Enable/Power Save input pin. Tie to ground to disable VDDQ. Tie to +5V to enable VDDQ and

11

EN/PSV activate PSAVE mode. Float to enable VDDQ and activate continous conduction mode. If floated,

bypass to VSSA with a 10nF capacitor.

12

NC

No Connect.

13

PGD

Power good output for VDDQ. PGD is low if VDDQ is outside the power good thresholds. This

pin is an open drain NMOS output and requires an external pull-up resistor.

14,15

VDDP +5V supply voltage input for the VDDQ gate drivers.

© 2006 Semtech Corp.

7

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