SI5316 查看數據表（PDF） - Silicon Laboratories

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SI5316

PRECISION CLOCK JITTER ATTENUATOR

Silicon Laboratories 

Si5316

Table 5. PCB Land Pattern Dimensions

Dimension

MIN

MAX

e

0.50 BSC.

E

5.42 REF.

D

5.42 REF.

E2

4.00

4.20

D2

4.00

4.20

GE

4.53

—

GD

4.53

—

X

—

0.28

Y

0.89 REF.

ZE

—

6.31

ZD

—

6.31

Notes (General):

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on IPC-SM-782 guidelines.

4. All dimensions shown are at Maximum Material Condition (MMC). Least Material

Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.

Notes (Solder Mask Design):

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the

solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.

Notes (Stencil Design):

1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be

used to assure good solder paste release.

2. The stencil thickness should be 0.125 mm (5 mils).

3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.

4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the

center ground pad.

Notes (Card Assembly):

1. A No-Clean, Type-3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification

for Small Body Components.

Preliminary Rev. 0.24

13

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