SIP11203DB 查看數據表（PDF） - Vishay Semiconductors

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SIP11203DB

SiP11203 Demonstration Board

Vishay Semiconductors 

SiP11203DB

Vishay Siliconix

Where CTR is the current transfer ratio of the opto-

coupler, and where R5 = R6, R8 = R7, C25 = C1 and

C29 = C2.

An origin pole, two zeroes and two poles can be poten-

tially synthesized. Hence, either Type 2 or Type 3 com-

pensation can be implemented. In the demonstration

board, Type 2 compensation is implemented, resulting

in a bandwidth in the region of 10 kHz. The transient

response of the output voltage to 5 A load steps is

depicted in Figure 11.

Startup and Shutdown

The startup sequence is described as follows:

1. The primary side duty cycle ramps up from its min-

imum value at rate determined by the charging of

the soft-start capacitor C20. At this point, the con-

verter is operating open loop.

2. Simultaneously, the bias voltage VIN for the

SiP11203 increases as decoupling capacitor C8 is

charged from SRH and SRL through the pulse

transformer. Regulated voltage VL also increases

as C8 is charged.

3. Once the voltage on the VL pin of the SiP11203 has

reached 3.5 V, the internal circuitry on the IC (apart

from output drivers) becomes functional, and the

converter begins to regulate. However, the refer-

ence voltage is still at zero.

4. When VL reaches 4.5 V, the reference voltage

ramps towards 1.225 V, at rate determined by the

charging of C5. The output voltage should then

track the reference voltage increase.

The various time constants described above must be

designed and synchronized to ensure a smooth star-

tup sequence for the converter. The SiP11203 also

incorporates a functionality whereby the on-time of the

synchronous MOSFETs is increased gradually at star-

tup, in order to minimize oscillation and steps in the

output voltage. This is the phase-in function of

SiP11203. This is accomplished by variation of R10.

This functionality is disabled if the RDEL pin of the

SiP11203 is tied to VL, by connecting a zero ohm link

in the R33 position. In Figure 12(a), the two distinct

stages of startup can be seen, where the output initially

rises open loop, and subsequently follows the refer-

ence voltage.

The SiP11203 incorporates a controlled shutdown fea-

ture, whereby the gates of the synchronous MOSFETs

are pulled to ground gradually once it is ascertained

that a shutdown event has indeed occurred. This pre-

vents destructive under-voltage transients due to LC-

filter oscillation that normally occurs on shutdown

when both gate voltages remain high. Variation of the

shutdown detection time and gate discharge time is

accomplished by variation of R12 and C6. The con-

trolled shutdown and minimal under-voltage swing are

depicted in Figure 12(b). The maximum under-voltage

seen is 0.7 V.

Output Voltage

(200 mV/DIV)

Output Voltage

(200 mV/DIV)

50.0 µS/DIV

(a)

50.0 µS/DIV

(b)

Figure 11. (a) Output voltage response to 5 A step load increase (b) Output voltage response to 5 A step load decrease (both ac coupling;

200 mV/div- 12.5 A ↔ 7.5 A, 48 V input, 200 mA/µS slew rate)

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Document Number: 74254

S-60997–Rev. A, 12-Jun-06

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