MX29L3211MC-10 查看數據表（PDF） - Macronix International

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MX29L3211MC-10

32M-BIT [4M x 8/2M x 16] CMOS SINGLE VOLTAGE PAGEMODE FLASH EEPROM

Macronix International 

LOW VCC WRITE INHIBIT

To avoid initiation of a write cycle during VCC power-up

and power-down, a write cycle is locked out for VCC less

than VLKO(typically 1.8V). If VCC < VLKO, the command

register is disabled and all internal program/erase circuits

are disabled. Under this condition the device will reset

to the read mode. Subsequent writes will be ignored until

the VCC level is greater than VLKO. It is the user's

responsibility to ensure that the control pins are logically

correct to prevent unintentional write when VCC is

above VLKO.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 10ns (typical) on CE or WE will

not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL,CE =

VIH or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

MX29L3211

P/N:PM0641

REV. 0.3, NOV. 06, 2001

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