MX29F800T/B
AUTOMATIC CHIP ERASE TIMING WAVEFORM
All data in chip are erased. External erase verification
is not required because data is erased automatically
by internal control circuit. Erasure completion can be
verified by DATA polling and toggle bit checking after
automatic erase starts. Device outputs 0 during era-
sure and 1 after erasure on Q7.(Q6 is for toggle bit; see
toggle bit, DATA polling, timing waveform)
AUTOMATIC CHIP ERASE TIMING WAVEFORM (WORD MODE)
Vcc 5V
A11~A18
A0~A10
WE
CE
OE
Q0,Q1,
Q4(Note 1)
Q7
555H
2AAH
555H
555H
2AAH
555H
tAS
tCWC
tAH
tCEPH1
tAETC
tCEP
tDS tDH
Command In Command In
Command In
Command In
Command In
Command In
DATA polling
Command In
Command #AAH
(Q0~Q7)
Command In
Command #55H
Command In
Command #80H
Command In
Command #AAH
Command In
Command #55H
Command In
Command #10H
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
P/N:PM0578
REV. 1.7, JUL. 24, 2001
20