HI-6010 查看數據表（PDF） - Holt Integrated Circuits

零件编号

产品描述 (功能)

生产厂家

HI-6010

ARINC 429 transmitter/receiver for 8 bit bus

Holt Integrated Circuits 

HI-6010

ABSOLUTE MAXIMUM RATINGS

(Voltages referenced to VSS = 0V)

Supply Voltage:

VDD

-0.5V to +7.0V Power Dissipation

PD

500mW

Input Voltage Range VIN

Input Current

IIN

Output Current

IOUT

-0.5V to VDD +0.5V

+10mA

+25mA

Operating Temperature Range:

Storage Temperature Range:

Lead Temperature

TA (Industrial)

-40°C to +85°C

TA (Hi temp & Military) -55°C to +125°C

TSTG

-65°C to +150°C

TLEAD

300°C for 60 Seconds

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings

only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is

not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS

VDD = 5.0V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified).

PARAMETER

SYMBOL

CONDITION

Operating Voltage

VDD

Min. Input Voltage (HI)

VIH

Max. Input Voltage (LO)

VIL

Min. Input Current (HI)

IIH

VIH = 4.9V

Max. Input Current (LO)

IIL

VIL = 0.1V

Min. Output Voltage (HI)

VOH

IOUT = -1.5mA

Max. Output Voltage (LO)

VIH

IOUT = 1.8mA

Operating Current Drain

IDD

f = 400KHz

Input Capacitance

CIN

Not tested

AC ELECTRICAL CHARACTERISTICS

VDD = 5.0V, VSS = 0V, TA =Operating Temperature Range (unless otherwise specified).

PARAMETER

SYMBOL

DATA BUS TIMING - READ

Setup C/D to RD

Hold C/D to RD

Delay RD to Data

Delay Data Bus Hi-Z from RD

Setup CS to RD

Hold RD to CS

DATA BUS TIMING - WRITE

Set C/D to WE

Hold C/D to WE

Setup Data Bus to WE

Hold Data Bus to WE

Setup CS to WE

Hold CS to WE

Pulse Width WE

TRANSMITTER TIMING

Delay TXE from CTS

Delay TXRDn from CTS

Delay TXRDY from last TXDn

Delay TXE from last TXDn

CTS pulse width

RECEIVER TIMING

Delay Last RXDn to RXRDY

(See Figure 1.)

(See Figure 2.)

(See Figure 3.)

(See Figure 4.)

tCDS

tCDH

tRC

tRD

tCSSR

tCSHR

tCDS

tCDH

tWDS

tDWH

tCSSW

tCSHW

tWP

tCTL

tENDAT

tTXRDY

tTDTX

tCPW

tDR

MIN

4.5

2.1

-1.5

2.7

TYP

5

1.4

1.4

0.8

MAX

5.5

0.7

1.5

0.7

2.8

20

UNITS

V

V

V

µA

µA

V

V

mA

pF

MIN

50

0

0

0

0

0

200

100

0

0

200

1.5

1

16

1

TYP

4

MAX

UNITS

ns

ns

200

ns

150

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

2.0

CLKS

CLK

CLKS

DATA BITS

CLK

3

CLKS

HOLT INTEGRATED CIRCUITS

4-12

Share Link: