VSC8110GB2 查看數據表（PDF） - Vitesse Semiconductor

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VSC8110GB2

ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation

Vitesse Semiconductor 

VSC8110

VITESSE

ATM/SONET/SDH 155/622 Mb/s Transceiver

Mux/Demux with Integrated Clock Generation

Data Sheet

Application Notes

2 Volt Supply Generation From 5 Volts

The 2 volt supply can be generated from the 5 volt supply using a linear regulator. There are many manufac-

turers who supply linear regulators. Refer to Table 17 for examples.

Table 17: Recommended 2 Volt Voltage Regulator

Recommended Regulator

REG1117

LT117A

Maximum Supply Current

800mA

800mA

Manufacturer’s Information

Burr Brown

800-548-6132

Linear Technology

Interconnecting the Byte Clocks (TXLSCKOUT and TXLSCKIN)

The byte clock (TXLSCKOUT and TXLSCKIN) on the VSC8110 has been brought off-chip to allow as

much flexibility in system-level clocking schemes as possible. Since the byte clock (TXLSCKOUT) clocks both

the VSC8110 and the UNI devices, it is important to pay close attention to the routing of this signal. The UNI

device in general is a CMOS part which can have very wide spreads in timing (1-11ns clock in to parallel data

out for the PM5355), which utilizes most of the 12.86ns period (at 78Mhz), leaving little for the trace delays

and set-up times required to interconnect the 2 devices. The recommended way of routing this clock when used

in a 622Mhz mode is to daisy chain it to the UNI device pin and then route it back to the VSC8110 along with

the byte data. This eliminates the 1-way trace delay that would otherwise be encountered between the data and

clock and thus leaves 1.86ns for the VSC8110 setup time and for variations in trace delays and rise times

between clock and data. The trace delay must be kept under 2ns (allowing an additional 1ns for variations in rise

times and skews) to ensure proper muxing of parallel input data into the VSC8110; reference Table 3 and 4.

AC Coupling and Terminating High-speed I/Os

The high speed signals on the VSC8110 (RxDATAIN, RxCLKIN, TxDATAOUT, TxCLKOUT) use VECL

levels which are essentially ECL levels shifted positive by 2 volts. The VECL I/Os are referenced to the VMM

supply and are terminated to ground. Since most optics modules use either ECL or PECL levels, the high speed

ports need to be ac coupled to overcome the difference in dc levels. In addition, the inputs must be dc biased to

hold the inputs at their threshold value with no signal applied. The dc biasing and 50 ohm termination require-

ments can easily be integrated together using a thevenin equivalent circuit as shown in Figure 8. The figure

shows the appropriate termination values when interfacing PECL to VECL and VECL to PECL. This network

provides the equivalent 50 ohm termination for the high speed I/Os and also provides the required dc biasing for

both the drivers and receivers. Table 18 contains recommended values for each of the components.

Layout of the 622 Signals

The routing of the 622 signals should be done using good high speed design practices. This would include

using controlled impedance lines and keeping the distance between components to an absolute minimum. In

addition, stubs should be kept at a minimum as well as any routing discontinuities. This will help minimize

reflections and ringing on the high speed lines and insure the maximum eye opening. In addition the output pull

Page 18

® VITESSE Semiconductor Corporation

G51011-0, Rev. 1.5

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