SPT7750A 查看數據表（PDF） - Cadeka Microcircuits LLC.
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SPT7750A Datasheet PDF : 8 Pages
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ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
Negative Supply Voltage (VEE TO GND) –7.0 to +0.5 V
Ground Voltage Differential .................... –0.5 to +0.5 V
Input Voltage
Analog Input Voltage ............................... +0.5 V to VEE
Reference Input Voltage .......................... +0.5 V to VEE
Digital Input Voltage ................................ +0.5 V to VEE
Reference Current VRT to VRB ........................... 35 mA
Output
Digital Output Current ............................... 0 to –28 mA
Temperature
Operating Temperature, ambient ............ –25 to +85 °C
case .......................... +125 °C
junction ...................... +150 °C
Lead Temperature, (soldering 10 seconds) ...... +300 °C
Storage Temperature ............................ –65 to +150 °C
Note: 1. Operation at any Absolute Maximum Rating is not implied. See
Electrical Specifications for proper nominal applied conditions
in typical applications.
ELECTRICAL SPECIFICATIONS
TJ = TC = TA = +25 °C , VEE=–5.2 V, VRB=–2.0 V, VRM=–1.0 V, VRT=0.00 V, ƒCLK=500 MHz, Duty Cycle=50%, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
SPT7750A
SPT7750B
LEVEL MIN TYP MAX MIN TYP MAX UNITS
Resolution
8
8
Bits
DC Accuracy
Integral Linearity Error (ILE)
Differential Linearity Error
(DLE)
No Missing Codes
ƒCLK = 100 kHz
ƒCLK = 100 kHz
I
–1.0
+1.0 –1.5
+1.5 LSB
I
–0.85
+0.95 –0.95
+1.5 LSB
Guaranteed
Guaranteed
Analog Input
Input Voltage Range
Input Bias Current
Input Resistance
Input Capacitance
Input Bandwidth
Small Signal
Large Signal
Offset Error VRT
Offset Error VRB
Input Slew Rate
Clock Synchronous
Input Currents
Reference Input
Ladder Resistance
Reference Bandwidth
I
VIN=0 V
I
V
Over Full Input Range V
V
V
IV
IV
V
V
I
V
VRB
VRT
VRB
VRT V
.75
2.0
.75
2.0 mA
15
15
kΩ
15
15
pF
900
900
MHz
500
500
MHz
–30
+30 –30
+30 mV
–30
+30 –30
+30 mV
5
5
V/ns
2
2
µA
60
80
30
60
80
30
Ω
MHz
Timing Characteristics
Maximum Sample Rate
Aperture Jitter
Acquisition Time
Clock to Data Delay
CLK to Data Ready Delay
I
500
500
MHz
V
2
2
ps
V
250
250
ps
IV
0.9
1.4
1.9
0.9
1.4
1.9 ns
IV 1.25 1.75 2.25 1.25 1.75 2.25 ns
Dynamic Performance
Signal-To-Noise Ratio
(without Harmonics)
ƒIN = 50 MHz
ƒIN = 250 MHz
Total Harmonic Distortion
ƒIN = 50 MHz
ƒIN = 250 MHz
Signal-to-Noise and Distortion
ƒIN = 50 MHz
ƒIN = 250 MHz
I
47
I
44
I
–46
I
–38
I
43
I
37
45
dB
42
dB
–44
dBc
–36
dBc
41
dB
35
dB
SPT7750
2
October 2002
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